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Projects in Awesome Lists tagged with network-on-chip

A curated list of projects in awesome lists tagged with network-on-chip .

https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 25 Oct 2024

https://github.com/sld-columbia/esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

accelerators asic embedded-systems fpga network-on-chip riscv system-on-chip

Last synced: 03 Nov 2024

https://github.com/ucb-bar/constellation

A Chisel RTL generator for network-on-chip interconnects

chisel hardware interconnect network-on-chip noc rtl soc

Last synced: 21 Dec 2024

https://github.com/taichi-ishitani/tnoc

Network on Chip Implementation written in SytemVerilog

amba amba-axi axi axi4 network-on-chip noc systemverilog uvm

Last synced: 17 Dec 2024

https://github.com/aignacio/ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

axi4 flits mpsoc network-on-chip noc router virtual-channels

Last synced: 03 Nov 2024

https://github.com/agalimberti/NoCRouter

RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

network-on-chip noc router systemverilog

Last synced: 03 Nov 2024

https://github.com/ueqri/vis4mesh

Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research

computer-architecture gpgpu network-analysis network-on-chip noc visualization

Last synced: 17 Nov 2024

https://github.com/amamory/hermes-trojan

Example of hardware trojan in a router detected with formal property verification

assertions formal-verification network-on-chip property-based-testing sva systemverilog trojan vhdl

Last synced: 21 Nov 2024

https://github.com/amamory/zynq-ps-hermes-noc

Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface

axi-stream axi4 network-on-chip noc tcl vivado xilinx zynq

Last synced: 21 Nov 2024

https://github.com/amamory/hermes-2x2-noc-axis-ip

A 2x2 mesh NoC compatible with AXI streaming interface

axi-stream axi4-stream network-on-chip vivado

Last synced: 21 Nov 2024

https://github.com/amamory/zynq-hermes-noc-demo

A demonstrator of Hermes network-on-chip communicating with the ARM processor

axi-stream axi4 network-on-chip router vivado zedboard zynq-7000

Last synced: 21 Nov 2024

https://github.com/amamory/hermes-router-axis-ip

A Vivado IP of Hermes network-on-chip router with AXI streaming interfaces

axis network-on-chip vhdl vivado xilinx

Last synced: 21 Nov 2024

https://github.com/mobink980/network-on-chip

As we transition into the era characterized by many-core architectures and the challenges posed by dark silicon, the design and implementation of highly efficient on-chip interconnects have become paramount. This repository is dedicated to the advancement of efficient Network-on-Chip (NoC) solutions within the gem5 simulator framework.

artificial-intelligence c-plus-plus garnet heterogeneous-systems many-core network-on-chip python

Last synced: 18 Dec 2024