Projects in Awesome Lists by ucb-bar
A curated list of projects in awesome lists by ucb-bar .
https://github.com/ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar
Last synced: 14 May 2025
https://github.com/ucb-bar/chisel-tutorial
chisel tutorial exercises and answers
Last synced: 12 Apr 2025
https://github.com/ucb-bar/riscv-sodor
educational microarchitectures for risc-v isa
Last synced: 15 May 2025
https://github.com/ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Last synced: 16 Mar 2025
https://github.com/ucb-bar/hammer
Hammer: Highly Agile Masks Made Effortlessly from RTL
Last synced: 15 May 2025
https://github.com/ucb-bar/dsptools
A Library of Chisel3 Tools for Digital Signal Processing
Last synced: 05 Apr 2025
https://github.com/ucb-bar/chiseltest
The batteries-included testing and formal verification library for Chisel-based RTL designs.
chisel formal testing verification
Last synced: 22 Apr 2025
https://github.com/ucb-bar/constellation
A Chisel RTL generator for network-on-chip interconnects
chisel hardware interconnect network-on-chip noc rtl soc
Last synced: 04 Apr 2025
https://github.com/ucb-bar/hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
Last synced: 10 Apr 2025
https://github.com/ucb-bar/esp-llvm
UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
Last synced: 13 Apr 2025
https://github.com/ucb-bar/midas
FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
Last synced: 13 Apr 2025
https://github.com/ucb-bar/saturn-vectors
Chisel RISC-V Vector 1.0 Implementation
chisel cpu microarchitecture risc-v rvv vectors
Last synced: 07 Apr 2025
https://github.com/ucb-bar/onnxruntime-riscv
Fork of upstream onnxruntime focused on supporting risc-v accelerators
Last synced: 13 Apr 2025
https://github.com/ucb-bar/cosa
A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
Last synced: 13 Apr 2025
https://github.com/ucb-bar/gemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
Last synced: 06 Apr 2025
https://github.com/ucb-bar/zscale
Z-scale Microarchitectural Implementation of RV32 ISA
Last synced: 13 Apr 2025
https://github.com/ucb-bar/chisel-gui
A prototype GUI for chisel-development
Last synced: 13 Apr 2025
https://github.com/ucb-bar/rose
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
Last synced: 13 Apr 2025
https://github.com/ucb-bar/hwacha-template
Template for projects using the Hwacha data-parallel accelerator
Last synced: 20 Apr 2025
https://github.com/ucb-bar/RoSE
A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.
Last synced: 22 Apr 2025
https://github.com/ucb-bar/shuttle
A Rocket-based RISC-V superscalar in-order core
Last synced: 13 Apr 2025
https://github.com/ucb-bar/baremetal-nn
Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.
c neural-network pytorch risc-v
Last synced: 13 Apr 2025
https://github.com/ucb-bar/libgloss-htif
A libgloss replacement for RISC-V that supports HTIF
Last synced: 13 Apr 2025
https://github.com/ucb-bar/asyncqueue
Lightweight re-packaging of AsyncQueue library from rocket-chip
Last synced: 13 Apr 2025
https://github.com/ucb-bar/nvdla-wrapper
Wraps the NVDLA project for Chipyard integration
Last synced: 05 Mar 2025
https://github.com/ucb-bar/riscv-blas
Custom BLAS and LAPACK Cross-Compilation Framework for RISC-V
Last synced: 05 Mar 2025
https://github.com/ucb-bar/esp-isa-sim
Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
Last synced: 13 Apr 2025
https://github.com/ucb-bar/fpga-spartan6
Support for zScale on Spartan6 FPGAs
Last synced: 05 Mar 2025
https://github.com/ucb-bar/virgo
Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC
Last synced: 05 May 2025
https://github.com/ucb-bar/dosa
DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators
Last synced: 13 Apr 2025
https://github.com/ucb-bar/fixedpoint
Chisel Fixed-Point Arithmetic Library
Last synced: 13 Apr 2025
https://github.com/ucb-bar/rocket-dsp-utils
Tools for integrating DspTools components into a rocket-chip
Last synced: 13 Apr 2025
https://github.com/ucb-bar/aurora
Virtualized Accelerator Orchestration for Multi-Tenant Workloads
Last synced: 13 Apr 2025
https://github.com/ucb-bar/vaesa
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design
Last synced: 13 Apr 2025
https://github.com/ucb-bar/hammer-cadence-plugins
Hammer plugins for Cadence tools
Last synced: 13 Apr 2025
https://github.com/ucb-bar/firrtl-transform-tutorial
A template for developing custom FIRRTL transforms
Last synced: 13 Apr 2025
https://github.com/ucb-bar/baremetal-ide
A submodule of Chipyard https://github.com/ucb-bar/chipyard
Last synced: 05 Mar 2025
https://github.com/ucb-bar/context-dependent-environments
A Scala library for Context-Dependent Evironments
Last synced: 13 Apr 2025
https://github.com/ucb-bar/fpga-images-zedboard
prebuilt images for zedboard zynq fpga
Last synced: 05 Mar 2025
https://github.com/ucb-bar/hammer-synopsys-plugins
Hammer plugins for synopsys tools
Last synced: 13 Apr 2025
https://github.com/ucb-bar/midas-zynq
A zynq host-platform shell for midas generated simulators.
Last synced: 05 Mar 2025
https://github.com/ucb-bar/spec2017-workload
FireMarshal workload for SPEC2017
Last synced: 13 Apr 2025
https://github.com/ucb-bar/riscv-docker-images
Curated set of DockerFiles for RISC-V projects
Last synced: 05 Mar 2025
https://github.com/ucb-bar/nvdla-workload
Base NVDLA Workload for FireMarshal
Last synced: 13 Apr 2025
https://github.com/ucb-bar/esp-tests
Custom extensions to the RISC-V tests for the UCB-BAR ESP project
Last synced: 13 Apr 2025
https://github.com/ucb-bar/stac-top
The SRAM timing analysis chip for verifying SRAMs generated by SRAM22
Last synced: 13 Apr 2025
https://github.com/ucb-bar/pyuartsi
A standalone implementation of the Tethered Serial Interface (TSI) in Python.
Last synced: 13 Apr 2025
https://github.com/ucb-bar/baseband-modem
Digital baseband-modem processor for 2.4 GHz Bluetooth Low Energy and IEEE 802.15.4 standards
Last synced: 16 Jan 2025
https://github.com/ucb-bar/chipyard-toolchain-prebuilt
Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.
Last synced: 05 Mar 2025
https://github.com/ucb-bar/spike-devices
Collection of device models for spike
Last synced: 13 Apr 2025
https://github.com/ucb-bar/coremark-workload
FireMarshal workload for CoreMark EEMBC
Last synced: 13 Apr 2025
https://github.com/ucb-bar/riscv-coremark-pro
Compiles coremark-pro for riscv64 baremetal
Last synced: 05 Mar 2025
https://github.com/ucb-bar/opencl-kernels
OpenCL kernels for ucb-bar hardware
Last synced: 13 Apr 2025
https://github.com/ucb-bar/chisel-library-template
Use for developing Chisel+Firrtl libraries
Last synced: 05 Mar 2025
https://github.com/ucb-bar/vcd2step
Converts a VCD file to a Chisel tester input file
Last synced: 05 Mar 2025