Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by pulp-platform
A curated list of projects in awesome lists by pulp-platform .
https://github.com/pulp-platform/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Last synced: 30 Jul 2024
https://github.com/pulp-platform/pulpino
An open-source microcontroller system based on RISC-V
Last synced: 08 Aug 2024
https://github.com/pulp-platform/common_cells
Common SystemVerilog components
Last synced: 01 Aug 2024
https://github.com/pulp-platform/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
Last synced: 30 Jul 2024
https://github.com/pulp-platform/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
Last synced: 01 Aug 2024
https://github.com/pulp-platform/mempool
A 256-RISC-V-core system with low-latency access into shared L1 memory.
Last synced: 02 Aug 2024
https://github.com/pulp-platform/snitch
⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
Last synced: 31 Jul 2024
https://github.com/pulp-platform/bender
A dependency management tool for hardware projects.
Last synced: 01 Aug 2024
https://github.com/pulp-platform/riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
Last synced: 01 Aug 2024
https://github.com/pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
asic fpga riscv rtl-design simulation systemverilog
Last synced: 02 Aug 2024
https://github.com/pulp-platform/register_interface
Generic Register Interface (contains various adapters)
Last synced: 02 Aug 2024
https://github.com/pulp-platform/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
computer-architecture fpga heterogeneous-computing heterogeneous-parallel-programming iommu many-core-architectures openmp-offloading openmp-parallelization riscv shared-memory unified-virtual-memory
Last synced: 01 Aug 2024
https://github.com/pulp-platform/pulp_soc
pulp_soc is the core building component of PULP based SoCs
Last synced: 02 Aug 2024
https://github.com/pulp-platform/iDMA
A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
Last synced: 02 Aug 2024
https://github.com/pulp-platform/FlooNoC
A Fast, Low-Overhead On-chip Network
Last synced: 02 Aug 2024
https://github.com/pulp-platform/dory
A tool to deploy Deep Neural Networks on PULP-based SoC's
Last synced: 02 Aug 2024
https://github.com/pulp-platform/axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
Last synced: 02 Aug 2024
https://github.com/pulp-platform/bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
Last synced: 09 Aug 2024
https://github.com/pulp-platform/morty
A SystemVerilog source file pickler.
picklers rickandmorty rust systemverilog-hdl
Last synced: 02 Aug 2024
https://github.com/pulp-platform/spatz
Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
Last synced: 02 Aug 2024
https://github.com/pulp-platform/tech_cells_generic
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Last synced: 02 Aug 2024
https://github.com/pulp-platform/culsans
Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
Last synced: 02 Aug 2024