Projects in Awesome Lists by pulp-platform

https://github.com/pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog

Last synced: 07 Mar 2026

https://github.com/pulp-platform/pulpino

An open-source microcontroller system based on RISC-V

Last synced: 07 Feb 2026

https://github.com/pulp-platform/common_cells

Common SystemVerilog components

Last synced: 07 Feb 2026

https://github.com/pulp-platform/pulp-dronet

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

artificial-intelligence autonomous-quadcoptor closed-loop-control cnn deep-learning end-to-end-learning nano-uav pulp riscv

Last synced: 07 Feb 2026

https://github.com/pulp-platform/ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ara asic cpu riscv rv64gcv rvv vector

Last synced: 07 Feb 2026

https://github.com/pulp-platform/pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Last synced: 07 Feb 2026

https://github.com/pulp-platform/pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

Last synced: 07 Feb 2026

https://github.com/pulp-platform/bender

A dependency management tool for hardware projects.

Last synced: 21 Oct 2025

https://github.com/pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

asic fpga riscv rtl-design simulation systemverilog

Last synced: 07 Feb 2026

https://github.com/pulp-platform/mempool

A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

asic manycore risc-v

Last synced: 07 Feb 2026

https://github.com/pulp-platform/riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

debug riscv

Last synced: 03 Mar 2026

https://github.com/pulp-platform/snitch

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

Last synced: 16 Mar 2025

https://github.com/pulp-platform/croc

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

asic riscv rtl-design systemverilog

Last synced: 07 Feb 2026

https://github.com/pulp-platform/register_interface

Generic Register Interface (contains various adapters)

Last synced: 07 Feb 2026

https://github.com/pulp-platform/snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

Last synced: 07 Feb 2026

https://github.com/pulp-platform/pulp-sdk

Last synced: 07 Feb 2026

https://github.com/pulp-platform/pulp_cluster

The multi-core cluster of a PULP system.

Last synced: 07 Feb 2026

https://github.com/pulp-platform/carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

asic c fpga heterogeneous-computing mixed-criticality-systems riscv safety-critical simulation systemverilog

Last synced: 07 Feb 2026

https://github.com/pulp-platform/hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

computer-architecture fpga heterogeneous-computing heterogeneous-parallel-programming iommu many-core-architectures openmp-offloading openmp-parallelization riscv shared-memory unified-virtual-memory