Projects in Awesome Lists tagged with testbenches
A curated list of projects in awesome lists tagged with testbenches .
https://github.com/VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
altera asic fpga hardware-designs hardware-libraries hardware-modules lattice osvvm poc-library python regression-testing simulation synthesis testbenches uvvm verification vhdl vlsi vunit xilinx
Last synced: 22 Apr 2025
https://github.com/BrianHGinc/BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
altera ddr3 fpga hdl intel lattice systemverilog testbenches verilog xilinx
Last synced: 15 Jun 2025
https://github.com/w531t4/fpga_led_display
Use FPGA to drive large LED matrixes at high speeds!
ecp5 fpga led matrix rgb24 spi systemverilog testbenches uart ulx3s verilog
Last synced: 23 Jan 2026
https://github.com/istiak8empire/hands-on-project-of-verilog-hdl
Implementing Hands-on Project of Verilog-HDL
altera arm asic asic-design async fpga intel logic-gates modeling modelsim simulation synthesis systemverilog testbenches verification verilog verilog-hdl vhdl xilinx xilinx-fpga
Last synced: 02 Mar 2026
https://github.com/mcleber/verilog_testbench_essentials
Creating testbenches in Verilog is an essential practice to verify the functionality of your modules and ensure your design behaves as expected.
learning-verilog testbench testbenches verilog verilog-hdl verilog-testbenches
Last synced: 24 Jan 2026
