Projects in Awesome Lists tagged with processor-architecture
A curated list of projects in awesome lists tagged with processor-architecture .
https://github.com/intel/pcm
Intel® Performance Counter Monitor (Intel® PCM)
cpu energy freebsd intel linux monitor-performance monitoring osx pcm performance-analysis performance-counters performance-dashboard performance-metrics performance-monitoring performance-visualization power processor processor-architecture windows xeon
Last synced: 13 May 2025
https://github.com/mortbopet/ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
computer-architecture cpu-emulator education processor-architecture qt risc risc-v simulator
Last synced: 14 May 2025
https://github.com/mortbopet/Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
computer-architecture cpu-emulator education processor-architecture qt risc risc-v simulator
Last synced: 25 Mar 2025
https://github.com/jbush001/nyuziprocessor
GPGPU microprocessor architecture
fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog
Last synced: 15 May 2025
https://github.com/jbush001/NyuziProcessor
GPGPU microprocessor architecture
fpga gpu gpu-computing graphics hardware microprocessor processor-architecture verilog
Last synced: 14 Mar 2025
https://github.com/hlorenzi/customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
asm assembler assembly assembly-language bytecode bytecode-compiler compiler custom customizable instruction-set instruction-set-architecture machine-code microprocessor processor-architecture rust rust-lang user-defined virtual-machine vm webassembly
Last synced: 14 May 2025
https://github.com/mikeroyal/risc-v-guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization
Last synced: 05 Apr 2025
https://github.com/mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization
Last synced: 14 Mar 2025
https://github.com/alirezakay/risc-cpu
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-architecture cpu-model instruction-set-architecture isa mips-processor multi-cycle processor-architecture processor-design risc-processor vhdl vhdl-code vhdl-modules
Last synced: 16 Mar 2025
https://github.com/sdasgup3/parallel-processor-design
Super scalar Processor design
assembler bison branch-prediction bypassing flex forwarding instruction-level-parallelism instruction-set instruction-set-architecture mnemonics opcode parallel-computing pipeline-cpu pipeline-processor processor processor-architecture processor-simulator superscalar verilog verilog-hdl
Last synced: 12 Apr 2025
https://github.com/amey-thakur/computer-organization-and-architecture-and-processor-architecture-lab
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
amey ameythakur computer-engineering computer-organ computer-organisation computer-organisation-architechure computer-organization computer-organization-and-design computer-organization-lab computer-science engineering megasatish processor-architecture processor-design textbooks
Last synced: 25 Jan 2025
https://github.com/godtamit/tomasulo-simulation
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
hardware processor processor-architecture processor-simulator simulation tomasulo
Last synced: 15 Apr 2025
https://github.com/geekalexis/superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
mips processor-architecture verilog
Last synced: 02 Mar 2025
https://github.com/worthant/opd
:computer: This course is about computer science basics.
computer-architecture-fundamentals computer-science-basics microprocessors processor-architecture unix-like-os unix-os
Last synced: 12 Feb 2025
https://github.com/luk3sky/building-a-processor---project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
alu hdl processor-architecture verilog-hdl verilog-project
Last synced: 21 Mar 2025
https://github.com/arxiver/pipelined-mips
MIPS Pipelined CPU simulation using VHDL language
hardware-designs processor processor-architecture processor-simulator vhdl vhdl-code
Last synced: 04 Mar 2025
https://github.com/linguini1/gol-16
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
arm-assembly arm-processor assembler assembly emulator hardware hardware-design processor processor-architecture processor-arm schematic
Last synced: 11 Feb 2025
https://github.com/shyamal-anadkat/wisc-sp13
CS 552 term project : functional design of a microprocessor called the WISC-SP13
cs552 hardware-designs mips-assembly processor processor-architecture verilog verilog-hdl
Last synced: 16 Dec 2024
https://github.com/arda-guler/turnacore
An imaginary 16-bit CPU architecture with custom assembly language and instructions
asm assembly challenge cpu cpu-emulator educational emulator experimental low-level memory processor processor-architecture processor-simulator ram
Last synced: 02 May 2025
https://github.com/meiniki/rv32i_sc_logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
computer-science digital-design educational logisim logisim-evolution processor-architecture risc-v
Last synced: 16 Mar 2025
https://github.com/suyashmahar/urisc
Single instruction processor and toolchain
fpga processor-architecture systemverilog urisc
Last synced: 16 May 2025
https://github.com/z1skgr/vhdl-processor-charis
Architecture of processor designed in vhdl
boolean-algebra computer-architecture computer-architectures custom-commands forwarding hardware hazards isa logic-programming pipeline-processor processor-architecture vhdl
Last synced: 16 Mar 2025
https://github.com/furkankayar/deuarc
DEUARC RISC computer design in Quartus II 13.0
processor-architecture quartus2 risc
Last synced: 02 Mar 2025
https://github.com/helcsnewsxd/famaf-computer_science-computer_architecture-lab1
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
analysis armv8 assembly computer-architecture famaf-unc hardware-description-language lab pipelined-processor processor-architecture processor-design python quartus system-verilog university-project
Last synced: 28 Feb 2025
https://github.com/marcelofcandido/mult-processor
Project of a Verilog implementation of a multicycle processor for the discipline of Computer Architeture and Design II
computer-architecture multicycle-processor processor-architecture
Last synced: 14 May 2025
https://github.com/permutationlock/superscalar_processor
Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.
logisim processor-architecture superscalar
Last synced: 04 Mar 2025
https://github.com/icarogabryel/flote
Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.
computer-architecture computer-organization digital-circuits eletronics framework hardware-description-language hardware-designs hdl integrated-circuits processor-architecture python python-module simulation
Last synced: 23 Mar 2025
https://github.com/ubaidrmn/risc-v-assembly
RISC-V assembly code I wrote as part of my COAL course at UIT University.
assembly-language processor-architecture riscv rv32i
Last synced: 02 Apr 2025
https://github.com/helcsnewsxd/famaf-computer_science-computer_architecture-lab2
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
analysis armv8 assembly c famaf-unc hardware-description-language in-order-pipeline-architecture lab optimization out-of-order pipelined-processors processor processor-architecture processor-simulation python qemu quartus system-verilog university-project
Last synced: 28 Feb 2025
https://github.com/helcsnewsxd/famaf-computer_science-computer_architecture
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
armv8 computer-architecture famaf-unc hardware-description-language labs optimization pipelined-processors processor-architecture quartus system-verilog theory university-subjects
Last synced: 28 Feb 2025
https://github.com/guntas-13/mips-processor-basys3
Full FPGA Implementation of 32-bit FSM-based Multi-State MIPS Processor
mips-assembly mips-processor processor-architecture verilog
Last synced: 25 Mar 2025
https://github.com/damieng/binarycpu
Identify the processor architecture of binary files
npm pefile processor-architecture
Last synced: 05 Apr 2025
https://github.com/icarogabryel/flooat
HDL, simulator and Python framework. Designed to be friendly, simple, and productive. Easy to use and learn.
computer-architecture computer-organization digital-circuits eletronics framework hardware-description-language hardware-designs hdl integrated-circuits processor-architecture python python-module simulation
Last synced: 12 Mar 2025
https://github.com/dzen-g-neere/8-bit-processor
8-bit Processor emulator designed and impemented using Java SE
computer-architecture java java-se oop processor-architecture ram-architecture swing
Last synced: 16 Mar 2025
https://github.com/jotavare/x86-assembly-nasm
Explored x86 assembly programming using NASM, dived into low-level coding and discovered the inner workings of computer hardware and software.
assembly binary nasm processor-architecture processor-modes registers x86-64
Last synced: 22 Feb 2025
https://github.com/elvircrn/mic-1
A microprocessor implemented in VHDL
fpga logic-programming processor-architecture vhdl xilinx
Last synced: 16 Mar 2025
https://github.com/kariricode-framework/kariricode-processor-pipeline
A flexible and extensible processor pipeline component for the KaririCode framework. Enables the creation of modular, configurable processing chains for data transformation, validation, and sanitization tasks
framework kariri-code php pipeline processor processor-architecture
Last synced: 16 Apr 2025
https://github.com/icarogabryel/sea-iv
SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.
assembler assembly assembly-language computer-organization instruction-set-architecture moon moon-iv processor processor-architecture
Last synced: 15 Mar 2025
https://github.com/harmim/vut-avs-labs
Architektury výpočetních systémů - Cvičení
avs openmp parallel-computing processor-architecture vectorized-computation vut vut-fit
Last synced: 31 Mar 2025
https://github.com/bpavan16/32-bit-processor-coa
This is a 32 Bit Processor design with 3 address format and indirect addressing
32-bit-processor computer-architecture logisim processor-architecture processor-design
Last synced: 10 Apr 2025
https://github.com/marcelofcandido/el-tomasulo
Implementation of Tomasulo's algorithm in Verilog for the Computer Architecture and Design II discipline
computer-architecture hardware processor-architecture tomasulo-algorithm
Last synced: 14 May 2025
https://github.com/cwielder/coldcpu
Custom processor architecture, assembly language, and toolchain.
assembler assembly compiler cpp cpu emulation premake processor-architecture
Last synced: 15 Mar 2025
https://github.com/samiyaalizaidi/pipelined-risc-v-processor
A Pipelined RISC-V Processor with forwarding support and hazard detection.
assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado
Last synced: 06 Mar 2025
https://github.com/astrogeekdk/risc-v-basic-simd
A basic implemention of 8 lane vector SIMD in RISC-V 5 Stage Pipeline, written in Chisel and Scala.
processor processor-architecture processor-design processor-simulator risc-v risc-v-assembly risc-v-emulator simd simd-parallelism
Last synced: 25 Mar 2025
https://github.com/elvircrn/80085
A microprocessor implemented in VHDL
fpga logic-programming processor-architecture vhdl xilinx
Last synced: 31 Dec 2024
https://github.com/skpro-glitch/riscv-processor-asic
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
asic asic-design asic-verification fpga hardware-designs open-source openlane openlane-flow processor-architecture processor-design risc-v riscv32 verilog verilog-hdl vlsi vlsi-design
Last synced: 06 Apr 2025
https://github.com/mtumilowicz/java17-mesi-false-sharing-processor-optimisations-workshop
Introduction to cache coherence: false sharing, MESI protocol and vectorization
cache-coherence cache-coherency cache-invalidation cache-line cache-line-padding false-sharing jmh jmh-benchmarks mesi mesi-protocol multi-core-architectures processor-architecture simd simd-instructions simd-programming vectorization workshop workshop-materials writeback writethrough
Last synced: 23 Feb 2025
https://github.com/zavierferodova/computation-challenge
Python script to fill your computer memory with processor bits word size
processor-architecture processor-maximum-access processor-memory-access
Last synced: 25 Feb 2025
https://github.com/sskender/ferrisc
RISC ARM7 Assembly
armv7 assembly fer processor processor-architecture processor-simulator processors risc risc-arm7-assembly risc-processor
Last synced: 22 Mar 2025
