Projects in Awesome Lists tagged with isa
A curated list of projects in awesome lists tagged with isa .
https://github.com/michaeljclark/rv8
RISC-V simulator for x86-64
binary-translation disassembler emulator histogram isa linux macro-op-fusion metadata risc riscv rv-jit rv-meta rv-sim rv-sys rv8 simulator
Last synced: 04 Apr 2025
https://github.com/mrlsd/riscv-fs
F# RISC-V Instruction Set formal specification
cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64
Last synced: 04 Apr 2025
https://github.com/mrLSD/riscv-fs
F# RISC-V Instruction Set formal specification
cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64
Last synced: 21 Apr 2025
https://github.com/nxbyte/ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
arm arm-legv8-simulator forwarding-unit hazard-detection hennessy isa ldr legv8-arm multi-cycle patterson pipeline-cpu single-cycle verilog vivado xilinx
Last synced: 21 Jul 2025
https://github.com/mrisc32/mrisc32
MRSIC32 ISA documentation and development
Last synced: 22 Jul 2025
https://github.com/hkzlab/es1868_isa8
ISA 8bit sound card based on the ES1868F sound chip, providing Sound Blaster PRO and OPL3 compatibility in a highly integrated package
audio dos isa retrocomputing soundcard
Last synced: 30 Mar 2025
https://github.com/nfdi4plants/swate
Excel Add-In for annotation of experimental data and computational workflows.
biology education isa minimal-information ontology rdm research-data-management
Last synced: 14 Apr 2025
https://github.com/hkzlab/es688_isa8
Sound Card for the ISA (8bit) bus sporting Sound Blaster / Sound Blaster PRO emulation via ES688F chip, and a real Yamaha OPL3 FM Synth. It's also completely jumper configurable.
audio dos isa openhardware retrocomputing retrogaming schematics soundblaster synth yamaha
Last synced: 30 Mar 2025
https://github.com/stnolting/neorv32-riscof
✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
ghdl isa neorv32 processor risc-v riscof riscv sail-riscv verification vhdl
Last synced: 30 Jul 2025
https://github.com/hkzlab/isa_ems_4mb
ISA 4Mb EMS expansion board
expansion homebrew isa pcxt retrocomputing schematics
Last synced: 12 Apr 2025
https://github.com/hkzlab/isa_8bitnetwork_8019
8bit ISA NE2000-compatible network card based on the RTL8019AS chip
hardware homebrew isa msdos ne2000 network retrocomputing
Last synced: 08 Oct 2025
https://github.com/hkzlab/isa_ega_chips
This board is and EGA clone based on a reversed PA-WTEGA card, based on the chipset by CHIPS (P82C435 + P82A436).
circuits dos ega hardware isa retrocomputing retrogaming schematics
Last synced: 05 Sep 2025
https://github.com/shalan/zx16
A 16-bit RISC-V Inspired ISA
assembler computer-architecture isa
Last synced: 30 Jul 2025
https://github.com/alirezakay/risc-cpu
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-architecture cpu-model instruction-set-architecture isa mips-processor multi-cycle processor-architecture processor-design risc-processor vhdl vhdl-code vhdl-modules
Last synced: 03 Jan 2026
https://github.com/hkzlab/cga_schematics
IBM Colour Graphics Adapter schematics redrawn in KiCad
cga ibm isa retrocomputing schematics
Last synced: 17 Oct 2025
https://github.com/hkzlab/isa_ems_2mb
ISA 8bit EMS 2Mb expansion card
circuit electronics expansion homebrew isa msdos retrocomputing
Last synced: 12 Apr 2025
https://github.com/marcin-chwedczuk/mega-iso-vga
Using an old 8-bit ISA VGA card with Arduino Mega
8bit arduino isa retrocomputing vga
Last synced: 10 Apr 2025
https://github.com/djanderson/riscv-5stage-simulator
A 5-stage pipelining RISC-V 32I simulator written in Rust.
isa pipelining risc-v rust simulator
Last synced: 27 Apr 2025
https://github.com/nfdi4plants/arctrl
Polyglot (.NET/JS/Python) library for management of Annotated Research Contexts (ARCs) using an in-memory representation and runtime-agnostic contract systems.
arc cwl fable-libraries fair-data fsharp isa rdm ro-crate
Last synced: 07 Apr 2025
https://github.com/hkzlab/isa_dualuartparport
8 bit ISA Parallel port + dual UART adapter
homebrew isa kicad pcb retrocomputing
Last synced: 28 Jun 2025
https://github.com/sondernextdoor/virtualmachine
Turing-complete 64-bit virtual machine written in C++ and C#
architecture assembler assembly cpp cpu csharp custom emulator filesystem gui instruction isa set simple virtual virtual-machine virtualization vm wpf
Last synced: 08 Apr 2025
https://github.com/heimskr/why
A somewhat esoteric instruction set architecture, plus an assembler, linker and VM. Not related to WebAssembly.
Last synced: 13 Apr 2025
https://github.com/hkzlab/isa_quaduart2
This 8-bit ISA board will provide 4 serial RS232 ports using a single 16C554 controller. 2 ports are exposed on an external bracket and 2 are on internal headers.
dos homebrew isa pcb rs232 schematics serial
Last synced: 12 Apr 2025
https://github.com/bihealth/altamisa
AltamISA: a Python API for ISA-Tab files
Last synced: 14 Dec 2025
https://github.com/rami-sabbagh/asm-19
ASM-19 is a fantasy assembly language which has been created during the lockdown days of the COVID-19 virus.
16-bit assembler assembly emulator fantasy isa language machine virtual-machine
Last synced: 15 May 2025
https://github.com/david-palma/mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
32-bit computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips mips32 multi-cycle single-cycle vhdl
Last synced: 22 Oct 2025
https://github.com/hkzlab/isa_quaduart
ISA 8-bit Quad serial adapter
hardware homebrew isa pcxt retrocomputing
Last synced: 24 Apr 2025
https://github.com/engineersbox/gbox16-gpu
Implementation of a custom GPU ISA microarchitecture called GBox16 based around NVIDIA and AMD microarchitectures
gbox16 gpgpu gpu isa microarchitecture parallel-computing simt verilog vhdl
Last synced: 04 Jan 2026
https://github.com/divergentclouds/minuend
An emulator for a 4-instruction ISA with 2 addressing modes inspired by subleq
Last synced: 19 Jul 2025
https://github.com/divergentclouds/riw-16
A fantasy computer with 16 instructions.
assembly fantasy-computer fantasy-console instruction-set-architecture isa
Last synced: 28 Nov 2025
https://github.com/openlabun/logisimweb
developer-tools html isa javascript js
Last synced: 11 Jul 2025
https://github.com/ryp/vim-gcn-isa
Vim syntax highlighting support for AMD's GCN ISA
Last synced: 20 Feb 2025
https://github.com/inspiaaa/micro8
An 8-bit RISC computer built in Digital with a custom ISA and general-purpose assembler.
8-bit assembler assembly computer-architecture digital isa java logic risc risc-v simulation
Last synced: 18 Sep 2025
https://github.com/z1skgr/vhdl-processor-charis
Architecture of processor designed in vhdl
boolean-algebra computer-architecture computer-architectures custom-commands forwarding hardware hazards isa logic-programming pipeline-processor processor-architecture vhdl
Last synced: 10 Jul 2025
https://github.com/podorozhny/isa-parallel-port-adapter
VHDL, ISA, LPT (IEEE 1284, Parallel Port) in compatibility mode (SPP)
ieee-1284 isa lpt parallel-port spp vhdl
Last synced: 03 Mar 2025
https://github.com/grachale/microarchitecture_RISC_V
Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.
assembly isa microarchitecture risc-v verilog
Last synced: 20 Sep 2025
https://github.com/openlabun/LogisimWeb
developer-tools html isa javascript js
Last synced: 15 Apr 2025
https://github.com/europ/VUTBR-FIT-ISA
VUTBR - FIT: ISA 2017/2018
fit isa pop3 pop3-server rfc1939 vut vutbr
Last synced: 11 Mar 2025
https://github.com/harshalmittal4/24-bit-risc-processor
Computer Architecture-MIPS Processor simulation in verilog with self developed ISA
Last synced: 23 Aug 2025
https://github.com/josedavidss/ce_architecture1.isa-app
This project is based on graphics and text generation app. This is the first individual project for the CE Architecture 1 course.
assembly isa nasm-assembly pysimplegui python sasm x86
Last synced: 24 Feb 2025
https://github.com/jmcph4/cpu
My attempt at a CPU simulator
architecture assembly c cpu instruction-set-architecture instructions isa machine-code processor simulation simulator
Last synced: 28 Oct 2025
https://github.com/openlabun/MIPSTranslator
https://openlab.uninorte.edu.co/mipsconverter
computer-architecture isa mips
Last synced: 15 Apr 2025
https://github.com/openlabun/mipstranslator
https://mipsconverter.openlab.uninorte.edu.co/
computer-architecture isa mips
Last synced: 15 Apr 2025
https://github.com/xstupi00/DNS-Export
Network Applications and Network Administration - Project - Export of DNS information using Syslog protocol
c dns dns-server isa network-analysis syslog vut vut-fit
Last synced: 01 May 2025
https://github.com/nguyenphuminh/90deg
90deg is an OISC centered around vector dot product and addition
90deg assembly counter-machine cpu esolang esoteric-language fractran interpreter isa maths minskys-machine node oisc register register-machine risc turing-complete urisc vector vm
Last synced: 18 Jul 2025
https://github.com/v1bh475u/fix8
8-bit fixed length instructions assembler and emulator
Last synced: 10 Jul 2025
https://github.com/wolgemoth/international-standard-atmosphere
A C++ port of Max Bernard's C# solution for calculating temperature, pressure and air density at a given altitude, according to the ISA.
atmosphere atmosphere-model cpp cpp17 density earth header-only header-only-library international-standards isa pressure temperature template templated templates
Last synced: 18 Aug 2025
https://github.com/europ/vutbr-fit-isa
VUTBR - FIT: ISA 2017/2018
fit isa pop3 pop3-server rfc1939 vut vutbr
Last synced: 15 May 2025
https://github.com/david-palma/mips-32bit-encoder
C implementation of a 32-bit assembly instruction encoder for MIPS processors, designed to convert MIPS assembly instructions into their corresponding machine code formats for execution on MIPS-based systems.
assembly assembly-to-machine c c-programming computer-architecture instruction-set-architecture instuctions-encoder isa machine-code mips-architecture mips-instructions mips-processor
Last synced: 26 Mar 2025
https://github.com/notkartikye/custom-isa-assembler-simulator
🛠️ RISC Assembler and Simulator for Custom ISAs
assembler assembly-language isa risc simulator
Last synced: 30 Oct 2025
https://github.com/aubstract/aublang_assembler
An assembler for my language AubLang, to be used with my Minecraft CPU
assembler assembly cpu isa minecraft redstone syntax-highlighting
Last synced: 26 Sep 2025
https://github.com/oagoulart/dot86
A class assignment to design the data path of a processor
class-assignment educational-project isa risc
Last synced: 22 Jun 2025
https://github.com/tommythorn/anti80
Anti80 is design exercise in a more compiler friendly architecture in roughly the same implementation budget as the Z80
Last synced: 05 Mar 2025
https://github.com/remexre/mpisa
An experimental ISA simulator for a message-passing ISA.
Last synced: 09 Apr 2025
https://github.com/dtcxzyw/llvm-inst-db
Instruction database extracted from LLVM source
asmjit assembler assembly compiler decompiler disassembler emulator isa llvm qemu
Last synced: 04 Sep 2025
https://github.com/316293/opcode
🚀 Build custom agents and manage Claude Code sessions with this powerful GUI app and toolkit for seamless development and secure background tasks.
aarch32 anthropic anthropic-claude asm calculator claude-code ethereum ide instruction instructions isa llm-code opcodes parsable reference solidity tauri web3
Last synced: 16 Oct 2025
https://github.com/proyectosingenieriauninorte/riscvtranslator
computer-architecture isa ricsv
Last synced: 21 Feb 2025
https://github.com/theleopard65/isa-imitation
This repository contains a simple C++ implementation of a Von-Neumann architecture simulator. The program mimics the behavior of a basic computer architecture that uses a single memory space for both instructions and data. Users can load programs, execute them, and view the current state of the memory and registers.
32-bit 64-bit ac architecture c-plus-plus data executable explained implementation ir isa mar mdr memory pc registers simulation von-neumann x64 x86
Last synced: 18 Mar 2025
https://github.com/octokerbs/fcen-organizaciondelcomputador-1
Sequential logic - Instruction set architecture - Micro programming - Input/Output - Analog/Digital and Digital/Analog conversion - Memory bus
cache circuits-simulator isa risc-v sequential-logic
Last synced: 11 Mar 2025
https://github.com/shalan/z16
A 16-bit RISC-V Inspired ISA
assembler computer-architecture isa
Last synced: 11 Mar 2025
https://github.com/alexfru/sedicipuv2
SediCiPUv2 CPU architecture
16-bit 7400 assembler assembly-language cpu homebrew-cpu isa logisim logisim-cpu logisim-evolution tests ttl
Last synced: 22 Feb 2025
https://github.com/layheng-hok/risc-v-cpu
RISC-V CPU: Single-Cycle Processor for RISC-V ISA Built in Verilog - SUSTech's project of course CS202: Computer Organization in Spring 2024 - Score: 104.5/100
assembly computer-architecture computer-organization cpu cs202 ego fpga instruction-set-architecture isa processor project risc-v sustech verilog
Last synced: 28 Oct 2025
https://github.com/nobodywasishere/ponyo
A framework for implementing ISA simulators for any number of ISAs, currently supporting a subset of LEGv8
Last synced: 29 Mar 2025
https://github.com/rainingcomputers/srp16
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog
Last synced: 07 Apr 2025
https://github.com/octokerbs/FCEN-OrganizacionDelComputador-1
Sequential logic - Instruction set architecture - Micro programming - Input/Output - Analog/Digital and Digital/Analog conversion - Memory bus
cache circuits-simulator isa risc-v sequential-logic
Last synced: 02 Nov 2025
https://github.com/openlabun/riscvtranslator
computer-architecture isa ricsv
Last synced: 21 Mar 2025
https://github.com/0xnu/trading212
An unofficial Go library for interacting with the Trading212 API.
cfd invest investment investment-analysis investment-portfolio investment-strategies isa stocks
Last synced: 02 Jul 2025
https://github.com/ddrcode/riscv-isa
RISC-V instructions model and disassembler written in Rust
disassembler isa risc-v rust rust-lang
Last synced: 28 Mar 2025
