Projects in Awesome Lists tagged with single-cycle
A curated list of projects in awesome lists tagged with single-cycle .
https://github.com/nxbyte/ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
arm arm-legv8-simulator forwarding-unit hazard-detection hennessy isa ldr legv8-arm multi-cycle patterson pipeline-cpu single-cycle verilog vivado xilinx
Last synced: 21 Jul 2025
https://github.com/phillbush/legv8
LEGv8 CPU implementation and some tools like a LEGv8 assembler
awk hennessy hennessy-and-patterson legv8 legv8-arm patterson pipeline-cpu pipeline-processor single-cycle single-cycle-processor verilog
Last synced: 02 Jan 2026
https://github.com/martinkindall/mips_cpu
Single Cycle 32 bit MIPS
basys3 basys3-fpga fpga mips mips-cpu single-cycle single-cycle-processor systemverilog
Last synced: 02 Feb 2026
https://github.com/david-palma/mips-32bit
Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.
32-bit computer-architecture hardware-description-language hardware-designs instruction-set-architecture isa mips mips32 multi-cycle single-cycle vhdl
Last synced: 22 Oct 2025
https://github.com/muhammadtalhasami/rv32i_single_cycle_logisim
An implementation of rv32i single cycle processor on logisim
assembly-language hardware hardware-designs logisim microprocessor rsic-v rtl rv32i rv32i-processor single-cycle single-cycle-processor
Last synced: 18 Feb 2026
https://github.com/aben20807/computer_organization
1052_計算機組織 COMPUTER ORGANIZATION
cache cpu datapath pipeline single-cycle verilog
Last synced: 08 Mar 2026
https://github.com/balos1/mips_single_cycle
This is project is a MIPS Single-Cycle processor with a cache for data memory.
computer-architecture mips-processor single-cycle
Last synced: 19 Mar 2026
https://github.com/jack74387/single-cycle-8-bit-cpu
Single-Cycle 8-bit CPU designed for basic instruction execution with Logisim.
circuit-design computer-organization-and-design cpu single-cycle
Last synced: 26 Feb 2026
