Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists tagged with basys3
A curated list of projects in awesome lists tagged with basys3 .
https://github.com/chili-chips-ba/openxc7-tetrisaraj
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
basys3 fpga gamedev nextpnr open-source rtl soc tetris-game verilog-hdl xc7a35t xilinx yosys
Last synced: 13 Dec 2024
https://github.com/j3soon/handwritten-digit-recognition-painter
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
artix-7 basys3 deep-learning hardware painter verilog
Last synced: 07 Dec 2024
https://github.com/raleighlittles/applied_digital_logic_exercises_using_fpgas
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
applied-digital-logic-exercises artix-7 basys3 fpga hdl microblaze-mcs verilog vivado
Last synced: 28 Nov 2024
https://github.com/romybompart/basys3-clock-alarm-with-buzzer
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
basys3 basys3-clock-alarm basys3-fpga buzzer buzzer-termination clock digilent digit digital-clock vhd vhdl-code
Last synced: 16 Nov 2024
https://github.com/raleighlittles/basys3countdownclock
Extremely basic countdown clock project for the Basys 3 FPGA development board.
basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx
Last synced: 28 Nov 2024
https://github.com/weisrc/nesv
NESystem Verilog
basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly
Last synced: 05 Nov 2024
https://github.com/mrtrkmn/digitaldesign
VHDL codes that are implemented on Basys 3 board.
Last synced: 25 Nov 2024
https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 axi axi-lite axi-memory-mapped axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado
Last synced: 16 Nov 2024
https://github.com/lucadibello/micro-alarm-system
🔐 A simple alarm system using Diligent Basys MX3 Microcontroller
alarm-system basys3 security-system
Last synced: 11 Nov 2024
https://github.com/barrettotte/thoth-rv32
Single cycle RISC-V core supporting most of RV32I
Last synced: 09 Dec 2024
