Projects in Awesome Lists tagged with basys3

https://github.com/j3soon/handwritten-digit-recognition-painter

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

artificial-intelligence artix-7 basys3 deep-learning digit-recognition embedded embedded-systems fpga handwritten-digit-recognition machine-learning neural-network painter verilog

Last synced: 07 Jan 2026

https://github.com/chili-chips-ba/openxc7-tetrisaraj

Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.

basys3 fpga gamedev nextpnr open-source rtl soc tetris-game verilog-hdl xc7a35t xilinx yosys

Last synced: 12 Jan 2026

https://github.com/martinkindall/mips_cpu

Single Cycle 32 bit MIPS

basys3 basys3-fpga fpga mips mips-cpu single-cycle single-cycle-processor systemverilog

Last synced: 02 Feb 2026

https://github.com/raleighlittles/applied_digital_logic_exercises_using_fpgas

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

applied-digital-logic-exercises artix-7 basys3 fpga hdl microblaze-mcs verilog vivado

Last synced: 29 Jan 2026

https://github.com/romybompart/basys3-clock-alarm-with-buzzer

Digital clock implemented in vhdl for the Basys 3 Board from Digilent.

basys3 basys3-clock-alarm basys3-fpga buzzer buzzer-termination clock digilent digit digital-clock vhd vhdl-code

Last synced: 09 Mar 2026

https://github.com/meiniki/logip

Logic Analyzer IP Core

amd asic basys3 digital formal-verification fpga hardware-description-language hdl ip logicanalyzer logip measurements ols sump symbiyosys systemverilog verilog vivado xilinx

Last synced: 03 Jan 2026

https://github.com/raleighlittles/basys3countdownclock

Extremely basic countdown clock project for the Basys 3 FPGA development board.

basys-3 basys3 fpga hdl seven-segment-display verilog vivado xdc xilinx

Last synced: 03 Jan 2026

https://github.com/martinkindall/risc-v-single-cycle

A Single Cycle Risc-V 32 bit CPU

basys3 basys3-fpga riscv riscv-assembly riscv32 rv32i single-cycle-processor systemverilog

Last synced: 02 Jan 2026

https://github.com/weisrc/nesv

NESystem Verilog

basys3 emscripten emulator fpga nes systemverilog verilator verilog vivado webassembly

Last synced: 18 Mar 2026

https://github.com/aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

artix artix-7 axi axi-lite axi-memory-mapped axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado

Last synced: 19 Mar 2026

https://github.com/eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado

Last synced: 25 Jan 2026

https://github.com/mrtrkmn/digitaldesign

VHDL codes that are implemented on Basys 3 board.

basys3 vhdl

Last synced: 04 Jan 2026

https://github.com/chrnthnkmutt/carpark_verilog

This project is using for illustrating on making the circuit on Xillin's BASYS3 from AMD and Verilog Language on Vivado, on the scope of car parking system

basys3 basys3-fpga fpga verilog verilog-code verilog-project