Projects in Awesome Lists tagged with vhdl-code
A curated list of projects in awesome lists tagged with vhdl-code .
https://github.com/alirezakay/risc-cpu
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-architecture cpu-model instruction-set-architecture isa mips-processor multi-cycle processor-architecture processor-design risc-processor vhdl vhdl-code vhdl-modules
Last synced: 16 Mar 2025
https://github.com/clarkfieseln/fpga_hw_sim_fwk_2
FPGA Hardware Simulation Framework
api emulation emulator fpga fpga-programming hdl pygubu pygubu-designer python python-3 python3 simulation simulator vhdl vhdl-code windows windows-10 windows-11 windows10
Last synced: 10 Nov 2024
https://github.com/mrtkp9993/vhdlexamples
VHDL examples.
embedded-software embedded-systems fpga vhdl vhdl-code
Last synced: 12 Mar 2025
https://github.com/arasgungore/256-colors-with-vga
A VHDL-based VGA driver to display 256 different colors on a monitor.
256-color 256-colors clock-divider color color-scheme colors colorscheme digital-design fpga fpga-board fpga-programming frequency-divider rgb rgb-color synchronization vga vga-controller vga-driver vhdl vhdl-code
Last synced: 09 Mar 2025
https://github.com/kazhuu/audio-synthesizer
Copy of old FPGA audio synthesizer project for DE2 development board
audio fpga synthesizer vhdl vhdl-code
Last synced: 18 Feb 2025
https://github.com/romybompart/basys3-clock-alarm-with-buzzer
Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
basys3 basys3-clock-alarm basys3-fpga buzzer buzzer-termination clock digilent digit digital-clock vhd vhdl-code
Last synced: 10 Mar 2025
https://github.com/arxiver/pipelined-mips
MIPS Pipelined CPU simulation using VHDL language
hardware-designs processor processor-architecture processor-simulator vhdl vhdl-code
Last synced: 04 Mar 2025
https://github.com/choaib-elmadi/getting-started-with-vhdl
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
circuit design digital fpga fpga-board fpga-programming fpga-soc hdl vhdl vhdl-code vhdl-examples
Last synced: 16 Mar 2025
https://github.com/soumyadip007/vhdl-modelsim-altera-simulator-coa
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.
computerarchitecture simulation vhdl-code
Last synced: 24 Feb 2025
https://github.com/benitoss/zxdos
Spartan 6 Lx16 Xilinx FPGA board implementing retro 80's 90's machines
Last synced: 13 Apr 2025
https://github.com/choaib-elmadi/working-with-fpga-and-vhdl
A collection of practical FPGA and VHDL projects using the ALTERA Cyclone V DE-1 SoC board.
electronics embedded-systems fpga fpga-board fpga-programming fpga-soc soc system-on-chip vhdl vhdl-code
Last synced: 22 Mar 2025
https://github.com/charlie5dh/risc-v-single-cycle-up
Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
fpga microprocessors quartus risc-v vhdl vhdl-code
Last synced: 26 Feb 2025
https://github.com/abdelazeem201/arm-core
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
amba armv4 armv6 armv7 armv9 axi c fpga soc systemverilog verilog vhdl vhdl-code
Last synced: 08 Apr 2025
https://github.com/tirtharajsinha/vhdl_codes
vhdl
adder circuit-design diagram logic-gate-simulator logic-gates subtractor truth-table universal-gate vhdl vhdl-code
Last synced: 23 Feb 2025
https://github.com/var7600/vhdl-generator
App that Generate VHDL Code and Testbench template file
vhdl vhdl-code vhdl-examples vhdl-language vhdl-modules vhdl-testbench
Last synced: 13 Apr 2025
https://github.com/alicepagano/mapd-a-project-ipbus-filter
FIR filter co-processor implementation in FPGA
Last synced: 16 Mar 2025
https://github.com/stavros/multiplier4bit
A 4bit Multiplier in VHDL
fpga full-adder half-adder vhdl vhdl-code vhdl-examples
Last synced: 11 Mar 2025
https://github.com/suvraneel/vhdl-xilinx
Projects were generated in Xilinx v14.7 If you're using Xilinx you may simply import the projects. Otherwise just read the codes in .vhd extensioned files. ☮️
Last synced: 24 Feb 2025
https://github.com/tremeschin/my-first-vhdl-even-or-odd
Blazing fast Even or Odd VHDL library
joke vhdl vhdl-code vhdl-testbench
Last synced: 26 Feb 2025
https://github.com/engineermichael/modelsim-altera-project-electronics-
⎔ Using the program ModelSim-Altera, to execute a Synchronous Counter with Asynchronous and Synchronous Reset project by implementing a 2 Bit, 4 Bit, 6 Bit, and 11 Bit for counters by using VHDL code.
altera-de1 altera-fpga altera-quartus modelsim synchronous-counter vhdl-code
Last synced: 22 Feb 2025
https://github.com/saeed-dev2/saeed-dev2
Config files for my GitHub profile.
assembly-language c config deep-learning deep-neural-networks devloper embedded-systems github-config machine-learning networking programming-language python reinforcement-learning vhdl-code vlsi-testing
Last synced: 03 Dec 2024
https://github.com/stavros/fsm_caralarm
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
finite-state-machine fpga fsm vhdl vhdl-code vhdl-examples
Last synced: 11 Mar 2025
https://github.com/eimon96/vhdl
logic-gates vhdl vhdl-code vhdl-coursework vhdl-testbench
Last synced: 13 Mar 2025
https://github.com/mostafagalal1/4-bit_bcd_counter
implementation of 4-bit BCD up/down counter. The counter work as follows: ● If input X = 0, the counter counts up. Otherwise, it counts down. ● If counting up, the counter’s value should be: 0000, 0001, 0010... ● If counting down: 0010, 0001, 0000...
design logic logic-gates vhdl vhdl-code
Last synced: 17 Mar 2025
https://github.com/mostafagalal1/full-adder-subtractor
4-bit ripple adder, which adds 2 4-bit inputs introducing sum and carry signals and implementing. 1. Half adder. 2. Full adder using the half adder. 3. 4-bit ripple adder/subtractor using the full adder.
design logic logic-gates vhdl vhdl-code
Last synced: 17 Mar 2025
https://github.com/azazhassankhan/vhdlcodecraft
Welcome to the "VHDL_Coding_Designs" repository, your gateway to the world of VHDL (VHSIC Hardware Description Language) and digital design. This is the space where hardware meets innovation, and digital concepts come to life. 🌐
designs dld hardware-description-language vhdl-code vivado
Last synced: 15 Mar 2025
https://github.com/var7600/vhdl93-docset
The VHDL93 Docset provides offline access to VHDL-93 documentation for users of Zeal and Dash. This docset includes syntax references, examples, and explanations of key VHDL concepts.
dash docset vhd vhdl vhdl-code vhdl-examples vhdl-language zeal
Last synced: 06 Mar 2025
https://github.com/stavros/4bitcounterparload
A 4bit Counter with Parallel Load including a Clock Divider and a BCD decoder
bcd counter fpga vhdl vhdl-code vhdl-examples
Last synced: 11 Mar 2025
https://github.com/mazen-daghari/vhdl-ams-sonde
description d'un capteur ECG a base de VHDL-AMS (SIMPLORER V7)
ecg-signal sensors simplorer vhdl-ams vhdl-code vhdl-language
Last synced: 06 Apr 2025
https://github.com/glock-atom/vhdl-multiplexer
electronics multiplexer vhdl vhdl-code
Last synced: 20 Feb 2025
https://github.com/humbertocg18/pucrs-fsd-2.3-2023.24
Trabalhos, Projetos, Exercícios e aulas realizados em VHDL e Assembly na cadeira de Fundamentos de sistemas digitais, matéria do segundo semestre.
asm assembly-language linux mars mips mips-assembly modelsim pucrs vhd vhdl vhdl-code wave
Last synced: 29 Mar 2025
https://github.com/seigtm/circuitry-spbpu-homework
This repository is dedicated to storing and managing homework assignments for the course "Digital Circuit Design: Modeling and Description Languages." The assignments primarily involve VHDL source code.
homework homework-assignments maxplus spbpu vhd vhdl vhdl-code vhdl-examples vhdl-language
Last synced: 23 Feb 2025
https://github.com/jn513/fpga_basics
Basic FPGA demo circuits made in Verilog HDL, VHDL and SystemVerilog
basic fpga learning verilog verilog-hdl vhdl vhdl-code
Last synced: 26 Feb 2025
https://github.com/lovc21/vhdl-code-from-lab
This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.
Last synced: 12 Mar 2025
https://github.com/codenkoffee/clock-simulation
VHDL simulation of a digital clock for the CSEN605 course at the German University in Cairo. Includes clock generation and stimulus processes.
Last synced: 20 Feb 2025
https://github.com/gracesevillano/rtic-project-antoine-s-army
This project not only provides hands-on experience with VHDL but also offers insight into the fundamental concepts of CPU architecture and design. It bridges the gap between theoretical knowledge and practical application, using the Nexys4 DDR board as a testbed
fpga-programming nexys4ddr vhdl-code
Last synced: 01 Mar 2025
https://github.com/sadegh15khedry/vhdl-projects
This repository contains various VHDL projects showcasing digital logic circuits implemented using VHDL.
and-gate c logical-gates nand-gate or-gate vhdl-code xor-gate
Last synced: 27 Feb 2025
https://github.com/dita-deb/vhdl_labs
All labs from CPE 3020 compiled into one single repository -Anindita
basys3-fpga tcl-scripts vhdl vhdl-code
Last synced: 18 Feb 2025
https://github.com/elecgeek/multisignalgene
Generates multi channels sounds from primitives
algorithms cordic-algorithm cplusplus-11 cplusplus-14 cplusplus-17 jackaudio state-machine stl vhdl-code wavegenerator
Last synced: 13 Mar 2025
https://github.com/itsuren/computerarchitecture
🏛️ [RUSHED🏃♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.
Last synced: 11 Mar 2025
https://github.com/man2dev/hardware-software-codesign-course
Some of my Hardware Software Codesign projects
co-design hardware-software-design university university-assignment university-course university-project vhdl vhdl-code
Last synced: 01 Mar 2025
https://github.com/elecgeek/pulsesgene
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
electronics fpga-programming ghdl hardware logic-circuit pcb-design spice vhdl vhdl-code yosys
Last synced: 11 Mar 2025
https://github.com/man2dev/computer-architecture-course
Some of my Computer Architecture projects
computer-architecture hdl mips university university-coursework university-projects vhdl vhdl-code xilinx xilinx-ise xilinx-ise-design-suite
Last synced: 01 Mar 2025
https://github.com/josefdc/laboratorio-fundamentos-de-electronica
Este repositorio es el hogar del curso de Fundamentos de Electrónica de la Universidad Tecnológica de Pereira. Aquí, los estudiantes y profesores pueden colaborar en el desarrollo y mejora continua del curso, compartiendo materiales didácticos, ejercicios prácticos, proyectos y más.
electronica universidad-tecnologica-pereira utp vhdl-code vhdl-coursework vhdl-examples
Last synced: 13 Apr 2025
