Projects in Awesome Lists tagged with tomasulo-algorithm
A curated list of projects in awesome lists tagged with tomasulo-algorithm .
https://github.com/skyzh/riscv-simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
branch-prediction cmake computer-architecture cpp cpu gtest pipeline riscv riscv-emulator riscv-simulator riscv32 speculation tomasulo-algorithm
Last synced: 16 Mar 2025
https://github.com/skyzh/RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
branch-prediction cmake computer-architecture cpp cpu gtest pipeline riscv riscv-emulator riscv-simulator riscv32 speculation tomasulo-algorithm
Last synced: 25 Mar 2025
https://github.com/cla7aye15i4nd/trivial-riscv-cpu
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
computer-architecture fpga pipeline riscv tomasulo-algorithm verilog-hdl
Last synced: 12 Mar 2025
https://github.com/giovaneiwamoto/tomasulo-simulator
🧲 Tomasulo Simulator - A speculative TFSim with a GUI. Implementation, evaluation, and validation of dynamic branch predictors.
Last synced: 29 Apr 2025
https://github.com/marcelofcandido/el-tomasulo
Implementation of Tomasulo's algorithm in Verilog for the Computer Architecture and Design II discipline
computer-architecture hardware processor-architecture tomasulo-algorithm
Last synced: 14 May 2025
