Projects in Awesome Lists tagged with sdram-controller
A curated list of projects in awesome lists tagged with sdram-controller .
https://github.com/ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
axi4 fpga sdram-controller verilog
Last synced: 03 May 2025
https://github.com/cw1997/sdram-controller
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
hardware hardware-designs sdram sdram-controller systemverilog verilog-project
Last synced: 04 Jan 2026
https://github.com/jakubcabal/sdram-tester-fpga
SDRAM Tester implemented in FPGA
cyc1000 fpga measures-throughput python sdram sdram-controller sdram-tester vhdl
Last synced: 04 Sep 2025
https://github.com/yasnakateb/sdramcontroller
🛠A SDRAM controller in Verilog HDL
icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl
Last synced: 19 Mar 2026
