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Projects in Awesome Lists tagged with sdram-controller
A curated list of projects in awesome lists tagged with sdram-controller .
https://github.com/ultraembedded/core_sdram_axi4
SDRAM controller with AXI4 interface
axi4 fpga sdram-controller verilog
Last synced: 12 Nov 2024
https://github.com/cw1997/sdram-controller
SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol
hardware hardware-designs sdram sdram-controller systemverilog verilog-project
Last synced: 28 Nov 2024
https://github.com/yasnakateb/sdramcontroller
🛠A SDRAM controller in Verilog HDL
icarus-verilog iverilog memory-controller sdram sdram-controller verilog verilog-hdl
Last synced: 19 Nov 2024
