Projects in Awesome Lists tagged with verilog-simulator
A curated list of projects in awesome lists tagged with verilog-simulator .
https://github.com/verilator/verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Last synced: 26 Mar 2025
https://github.com/f4pga/f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
architecture-definitions artix artix7 documentation fpga hdl ice40 kintex7 lattice primitives python sphinx symbiflow synthesis toolchain verilog verilog-simulations verilog-simulator vpr xilinx-fpga
Last synced: 22 Apr 2025
https://github.com/jeffdecola/my-verilog-examples
A place to keep my synthesizable verilog examples.
asic asic-design fpga gtkwave hardware hardware-architecture hardware-description-language hdl iverilog simulator synthesis synthesize systemverilog verilog verilog-simulator vivado waveform xilinx
Last synced: 30 Mar 2025
https://github.com/cw1997/verilog-parser
Verilog HDL Parser
parser parsers verilog verilog-hdl verilog-simulator
Last synced: 22 Mar 2025
https://github.com/jelhamm/verilog-hdl-codes-collection
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
7segment alu comparator counter decoder encoder gates multiplexer shiftregister testbench testbench-generator-verilog verilog verilog-hdl verilog-programs verilog-project verilog-simulator
Last synced: 04 Apr 2025
