https://github.com/skpro-glitch/parallel_multiplier

Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.

asic asic-design fpga fpga-programming multiplier parallel-multiplication register-transfer-level rtl rtl-design systemverilog systemverilog-test-bench verilog-hdl vlsi-design xilinx-vivado

Last synced: 20 Mar 2026