https://github.com/tariqjamel/image-processing-in-verilog

An image processing pipeline written in Verilog that performs RAW Bayer to RGB conversion and applies 3x3 convolution filters like blur and identity for pixel-level image enhancement.

image-processing modelsim pipeline pixel-processing rgb verilog vhdl xilinx xilinx-fpga

Last synced: 07 Feb 2026