Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by chipsalliance
A curated list of projects in awesome lists by chipsalliance .
https://github.com/chipsalliance/chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Last synced: 30 Jul 2024
https://github.com/chipsalliance/rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Last synced: 31 Jul 2024
https://chipsalliance.github.io/verible/
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Last synced: 30 Jul 2024
https://github.com/chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Last synced: 02 Aug 2024
https://github.com/chipsalliance/riscv-dv
Random instruction generator for RISC-V processor verification
Last synced: 31 Jul 2024
https://github.com/chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Last synced: 02 Aug 2024
https://github.com/chipsalliance/firrtl
Flexible Intermediate Representation for RTL
compiler firrtl hardware intermediate representation transformation
Last synced: 30 Jul 2024
https://github.com/chipsalliance/chisel-template
A template project for beginning new Chisel work
Last synced: 02 Aug 2024
https://github.com/chipsalliance/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
antlr antlr4-grammar elaboration linter parser parser-ast preprocessor python-api systemverilog uvm verilog vpi vpi-api vpi-standard
Last synced: 02 Aug 2024
https://github.com/chipsalliance/f4pga
FOSS Flow For FPGA
documentation sphinx symbiflow
Last synced: 02 Aug 2024
https://github.com/chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
compliance-testing hdl rtl symbiflow systemverilog verilog
Last synced: 02 Aug 2024
https://github.com/chipsalliance/f4pga-examples
Example designs showing different ways to use F4PGA toolchains.
conda-packages f4pga fpga fpga-designs litex symbiflow-toolchains verilog vexriscv
Last synced: 02 Aug 2024
https://github.com/chipsalliance/VeeRwolf
FuseSoC-based SoC for SweRV EH1 and EL2
Last synced: 09 Aug 2024
https://github.com/chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Last synced: 01 Aug 2024
https://github.com/chipsalliance/dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
Last synced: 02 Aug 2024
https://github.com/chipsalliance/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
ieee-standard listener serialization systemverilog vpi-api vpi-interface
Last synced: 02 Aug 2024
https://github.com/chipsalliance/aib-phy-hardware
Advanced Interface Bus (AIB) die-to-die hardware open source
Last synced: 01 Aug 2024
https://github.com/chipsalliance/caliptra
Caliptra IP and firmware for integrated Root of Trust block
Last synced: 03 Aug 2024
https://github.com/chipsalliance/fpga-tool-perf
FPGA tool performance profiling
arachne-pnr conda-environment f4pga fpga nextpnr perf performance-analysis symbiflow toolchain vpr yosys
Last synced: 03 Aug 2024
https://github.com/chipsalliance/fasm
FPGA Assembly (FASM) Parser and Generator
bitstream bitstream-format f4pga fasm fpga fpga-assembly parser symbiflow
Last synced: 02 Aug 2024
https://github.com/chipsalliance/omnixtend
OmniXtend cache coherence protocol
Last synced: 02 Aug 2024
https://github.com/chipsalliance/caliptra-rtl
HW Design Collateral for Caliptra RoT IP
Last synced: 03 Aug 2024
https://github.com/chipsalliance/AIB-specification
Home of the Advanced Interface Bus (AIB) specification.
Last synced: 02 Aug 2024
https://github.com/chipsalliance/cde
A Scala library for Context-Dependent Environments
Last synced: 02 Aug 2024
https://github.com/chipsalliance/firrtl-spec
The specification for the FIRRTL language
Last synced: 02 Aug 2024
https://github.com/chipsalliance/aib-phy-generator
AIB Generator: Analog hardware compiler for AIB PHY
Last synced: 09 Aug 2024
https://github.com/chipsalliance/rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
Last synced: 02 Aug 2024
https://github.com/chipsalliance/rocket-chip-fpga-shells
Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
Last synced: 02 Aug 2024
https://github.com/chipsalliance/rocket-chip-blocks
RTL blocks compatible with the Rocket Chip Generator
Last synced: 02 Aug 2024
https://github.com/chipsalliance/rocket
The working draft to split rocket core out from rocket chip
Last synced: 02 Aug 2024
https://github.com/chipsalliance/tree-sitter-firrtl
FIRRTL grammar for tree-sitter
Last synced: 04 Aug 2024
https://github.com/chipsalliance/rocket-pcb
PCB libraries and templates for rocket-chip based FPGA/ASIC designs
Last synced: 02 Aug 2024