Projects in Awesome Lists tagged with systemverilog-parser
A curated list of projects in awesome lists tagged with systemverilog-parser .
https://github.com/chipsalliance/verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Last synced: 14 May 2025
https://chipsalliance.github.io/verible/
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Last synced: 15 Mar 2025
https://github.com/nic30/hdlconvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser
Last synced: 15 May 2025
https://github.com/Nic30/hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
antrl4 fpga parser python systemverilog systemverilog-parser verilog verilog-parser vhdl vhdl-parser
Last synced: 15 Mar 2025