Projects in Awesome Lists by dpretet
A curated list of projects in awesome lists by dpretet .
https://github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
asic asic-design async cdc cross-clock-domain fifo fifo-cache fifo-queue fpga hdl icarus-verilog synthesis verification verilator verilog verilog-hdl
Last synced: 12 Jan 2026
https://github.com/dpretet/svut
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
flow foss gtkwave icarus-verilog mit-license python simulation simulator surfer svut systemverilog tdd tdd-utilities testcase vcd verification-methodologies verilator verilog
Last synced: 22 Apr 2025
https://github.com/dpretet/vim-leader-mapper
Vim plugin to create Neovim leader key menu
fzf leader-key neovim nvim vim-leader-mapper vim-plugin vim-script viml
Last synced: 12 Jul 2025
https://github.com/dpretet/svlogger
SystemVerilog Logger
asic class fpga hdl icarus logger logging simulation systemverilog verilog
Last synced: 06 Apr 2026