Projects in Awesome Lists tagged with synopsys
A curated list of projects in awesome lists tagged with synopsys .
https://github.com/limerainne/Dockerize-EDA
[WIP] Dockerize Synopsys/Cadence EDA tools
cadence dockerfile eda synopsys
Last synced: 21 Apr 2025
https://github.com/kaushalmodi/custom_uvm_report_server
Customized UVM Report Server
cadence synopsys systemverilog uvm vcs xcelium
Last synced: 06 Mar 2025
https://github.com/jenkinsci/synopsys-security-scan-plugin
Synopsys Security Plugin provides functionality for performing Security Scan with Black Duck, Coverity and Polaris.
blackduck coverity java jenkins-plugin polaris security-scan spring-integration synopsys
Last synced: 20 Jan 2025
https://github.com/parthpower/dcc_basic
Typical project for Synopsys DC Compiler
dc-compiler primetime synopsys tcl
Last synced: 09 Apr 2025
https://github.com/abdelazeem201/orca
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
asic asic-design fpga-soc hdl pnr rtl saed32nm synopsys synopsys-dc synopsys-iccii synopsys-vcs synthesis systemonchip upf verilog vhdl
Last synced: 08 Apr 2025
https://github.com/abdelazeem201/apb-i2s
I2S (Inter-IC Sound) interface module with APB (Advanced Peripheral Bus) interface signals. It has control logic for writing and reading data to/from a 4x32-bit FIFO and generates clock (sck), word select (ws), and serial data (sd) signals for I2S transmission.
apb asic fpga i2s synopsys vcs verilog
Last synced: 08 Apr 2025
https://github.com/abdelazeem201/cortex-m3-designstart-eval
Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.
arm asic cadence cortex-m3 fpga processor rtl simulation soc synopsys synthesis systemverilog verilog
Last synced: 08 Apr 2025
https://github.com/shenxianpeng/ansible-role-polaris
Ansible Role: Polaris - Installs and configures Polaris CLI
ansible ansible-playbook ansible-role polaris polaris-cli synopsys
Last synced: 06 Apr 2025
