Projects in Awesome Lists tagged with softcore

https://github.com/spinalhdl/vexriscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 14 May 2025

https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 14 Mar 2025

https://github.com/WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog

Last synced: 22 Apr 2025

https://github.com/howerj/forth-cpu

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c cpu forth fpga processor simulator softcore target-board vhdl

Last synced: 26 Dec 2025

https://github.com/agra-uni-bremen/microrv32

SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype

cpu fpga risc-v riscv rtl soc softcore spinalhdl verilog vhdl

Last synced: 20 Jan 2026

https://github.com/calint/tang-nano-9k--riscv--cache-psram

RISC-V implementation of RV32I for FPGA board Tang Nano 9K utilizing on-board burst PSRAM, flash and SD card

risc-v rv32i softcore systemverilog tang-nano-9k

Last synced: 04 Feb 2026

https://github.com/microdynamics-cpu/tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

chisel cpu processor riscv rt-thread rtl scala softcore verilator

Last synced: 21 Jul 2025

https://github.com/osresearch/risc8

Mostly AVR compatible FPGA soft-core

fpga ice40 microcontroller softcore up5k upduino yosys

Last synced: 05 Jan 2026

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of RV32I for FPGA board Tang Nano 20K utilizing on-board burst SDRAM, flash and SD card

risc-v rv32i softcore systemverilog tang-nano-20k

Last synced: 01 Mar 2026

https://github.com/darklife/udarkrisc

u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV

core cpu fpga processor processor-design risc rtl softcore verilog

Last synced: 11 Feb 2026

https://github.com/mcquerol/fsoc-sha1-niosii-implementation

SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.

c cyclone-5 fpga nios2 register-programming sha1 softcore systemverilog

Last synced: 16 Jun 2026

https://github.com/amanley97/23rv-core

Just a couple of nerds making a RISC-V Softcore

risc-v softcore systemverilog

Last synced: 31 Mar 2025

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