Projects in Awesome Lists tagged with memory-model
A curated list of projects in awesome lists tagged with memory-model .
https://github.com/ashvardanian/forkunion
Lower-latency OpenMP-style minimalistic scoped thread-pool designed for 'Fork-Join' parallelism in Rust and C++, avoiding memory allocations, mutexes, CAS-primitives, and false-sharing on the hot path 🍴
arm atomics compare-and-swap concurrency memory-model mpi multithreading openmp parallel-computing parallel-stl parallelism rayon thread-pool threadpool
Last synced: 16 Dec 2025
https://github.com/OSVVM/OSVVM
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
alerts constrained-random coverage coverage-bins memory memory-model methodology osvvm osvvm-blog scoreboard simulation testbench transaction-interfaces verification verification-methodologies vhdl
Last synced: 12 May 2025
https://github.com/ashvardanian/fork_union
Low(est?)-latency OpenMP-style minimalistic scoped thread-pool designed for 'Fork-Join' parallelism in Rust and C++, avoiding memory allocations, mutexes, CAS-primitives, and false-sharing on the hot path 🍴
arm atomics compare-and-swap concurrency memory-model mpi multithreading openmp parallel-computing parallel-stl parallelism rayon thread-pool threadpool
Last synced: 13 Jun 2025
https://github.com/johnwickerson/memalloy
Memory consistency modelling using Alloy
armv7 c11 compiler-design constraint-solver memory-model model-checking nvidia-gpus opencl powerpc x86
Last synced: 11 Jun 2025
https://github.com/wyvernsemi/mem_model
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
avalon axi cosimulation dpi-c ghdl memory-model nvc pli questasim simulation test-bench verilator verilog verilog-components verilog-testbenches vhdl vivado-simulator
Last synced: 08 Jan 2026
https://github.com/banyc/futex
Taming the beast of desync
atomics futex memory-model syncronization
Last synced: 27 Apr 2026