Projects in Awesome Lists by 0xabdellatif
A curated list of projects in awesome lists by 0xabdellatif .
https://github.com/0xabdellatif/sequencedetector
11001 sequence detector
asic digital-design fpga hardware hardware-description-language hdl sequence-detection sequence-detector verilog
Last synced: 27 Feb 2025
https://github.com/0xabdellatif/realtimeclocksystem
System that provides time & date for users in different languages
c18 datetime datetracker display embedded-c embedded-systems lcd microchip pic18f protocol real-time rtc rtc-module spi timetracker
Last synced: 27 Feb 2025
https://github.com/0xabdellatif/motor-controlling
Controlling Dc Motor Via Potentiometer
adc analog analog-to-digital-converter c18-compiler digital microchip motor pic18f pic18f452 pwm self-learning
Last synced: 27 Feb 2025
https://github.com/0xabdellatif/frequencydivider
verilog code for frequency divider circuit implemented with verilog hdl
digital-design fpga frequency-divider hardware-description-language hdl verilog
Last synced: 27 Feb 2025
https://github.com/0xabdellatif/skyguardian
unfinished game designed with raylib library
c game games gaming learning raylib sky-defender-game
Last synced: 27 Feb 2025
https://github.com/lemongrb/digitaldesignwithverilog
Simple circuits designed with verilog
asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects
Last synced: 27 Feb 2025