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Projects in Awesome Lists by PyHDI

A curated list of projects in awesome lists by PyHDI .

https://github.com/PyHDI/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

code-generator compiler control-flow-analyzer dataflow-analyzer hardware parser python verilog-hdl

Last synced: 09 Nov 2024

https://github.com/PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

compiler hardware hardware-construction-language high-level-synthesis python pyverilog verilog-hdl

Last synced: 26 Oct 2024

https://github.com/PyHDI/PyCoRAM

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

Last synced: 09 Nov 2024