https://github.com/PyHDI/Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

code-generator compiler control-flow-analyzer dataflow-analyzer hardware parser python verilog-hdl

Last synced: 18 Apr 2025

https://github.com/PyHDI/veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

compiler hardware hardware-construction-language high-level-synthesis python pyverilog verilog-hdl

Last synced: 15 Mar 2025

https://github.com/PyHDI/PyCoRAM

Python-based Portable IP-core Synthesis Framework for FPGA-based Computing

Last synced: 18 Apr 2025