Ecosyste.ms: Awesome
An open API service indexing awesome lists of open source software.
Projects in Awesome Lists by nishit0072e
A curated list of projects in awesome lists by nishit0072e .
https://github.com/nishit0072e/rtl-to-gdsii
Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation
gds2 openroad power time verilog-hdl yosys
Last synced: 01 Jan 2025
https://github.com/nishit0072e/sev_seg_fpga
its a seven segment display controller in FPGA which counts in ascending order
Last synced: 01 Jan 2025
https://github.com/nishit0072e/2bit-comparator
2 bit comparator design in transistor level in eSim software foremerly FreeCAD
Last synced: 01 Jan 2025
https://github.com/nishit0072e/view-only-pdf-download
With this JavaScript Script any view only protected pdf can be downloaded
Last synced: 01 Jan 2025
https://github.com/nishit0072e/tcp-calculator
A local server based TCP Calculator
Last synced: 01 Jan 2025
https://github.com/nishit0072e/vegetable_detection
An AI model has been implemented to detect potato, onion & tomato on a resource constrained hardware
ai edgeimpulse esp32cam oled-display-ssd1306 platformio-platform tensorflowlite-for-microcontrollers
Last synced: 01 Jan 2025
https://github.com/nishit0072e/rfid-toll-gate
A RFID Based Toll gate system is built using Aries v3 development board mounted with Vega Processor, Designed & Developed by CDAC INDIA
Last synced: 01 Jan 2025
https://github.com/nishit0072e/register_pipo_piso
Parallel in Parallel out, Parallel in Serial out Register Implementation with expansion Capabilities
Last synced: 01 Jan 2025
https://github.com/nishit0072e/nishit0072e
Config files for my GitHub profile.
Last synced: 01 Jan 2025
https://github.com/nishit0072e/sine_function
Sine function generator and plotting it on serial plotter
Last synced: 01 Jan 2025
https://github.com/nishit0072e/cisco_projects
A simple office Networking demo has been implemented using Cisco Packet Tracer to understand the networking topologies and working of corporate networks between machine to machine.
Last synced: 01 Jan 2025
https://github.com/nishit0072e/enc_dec_xor
8:3 Encoder is used as input and 3:8 decoder is used as output, to verify that the input and output data are same a Xor gate is implemented, it will return 1 if any mismatch in the input and output data and will 0 if all the bits of input and output match.
Last synced: 01 Jan 2025
https://github.com/nishit0072e/sev_seg_rev_fpga
A VERILOG code on seven segment display controller which counts in descending order
Last synced: 01 Jan 2025
https://github.com/nishit0072e/t_flipflop-using-vhdl
T FlipFlop is created with frequency divider in basys3 FPGA board of family Artix-7 with VHDL language
Last synced: 01 Jan 2025
https://github.com/nishit0072e/square_wave
Square wave generator and receiver
Last synced: 01 Jan 2025
https://github.com/nishit0072e/wifi_car
A code to operate a battery operated car over wifi control
Last synced: 01 Jan 2025
https://github.com/nishit0072e/nodemcu_ip
A Code to find ip address of a nodemcu-ESP8266
Last synced: 01 Jan 2025
https://github.com/nishit0072e/nav_list_hover_animation
An animation is shown during hovering cursor
Last synced: 01 Jan 2025
https://github.com/nishit0072e/full_adder-using-vhdl
Full adder program using VHDL language
Last synced: 01 Jan 2025
https://github.com/nishit0072e/google_home_automation
By this code you can control your home appliences by a nodemcu :
Last synced: 01 Jan 2025
https://github.com/nishit0072e/myself
a brief intro about myself using basic html
Last synced: 01 Jan 2025
https://github.com/nishit0072e/binary_input_fpga
A Verilog code on Binary input and display output in 7 segment display in FPGA
Last synced: 01 Jan 2025
https://github.com/nishit0072e/bin_2_bcd
Binary input BCD output in onboard 7-segment display of basys3
Last synced: 01 Jan 2025
https://github.com/nishit0072e/vsd-mini
This Repository solely made for the Research Internship using VSDSquadron Mini RISC-V Development Board
ch32v003 codespaces microcontroller platformio risc-v virtualbox
Last synced: 24 Dec 2024