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Projects in Awesome Lists tagged with arithmetic-logic-unit

A curated list of projects in awesome lists tagged with arithmetic-logic-unit .

https://github.com/cyber-anubis/the-hack-general-purpose-computer

Using HDL, from Boolean algebra and elementary logic gates to building a Central Processing Unit, a memory system, and a hardware platform, leading up to a 16-bit general-purpose computer. Then, implementing the modern software hierarchy designed to enable the translation and execution of object-based, high-level languages on a bare-bone computer hardware platform; Including Virtual machine,Compiler and Operating system.

arithmetic-logic-unit assembler compiler computer-architecture cpu hardware-description-language machine-language nand nand2tetris operating-system virtual-machine

Last synced: 25 Jan 2026

https://github.com/hoangsonww/digital-design-labs

🖥️ A collection of SystemVerilog modules and Assembly programs. This repo includes examples of decoders, encoders, binary adders, and interactive games such as Guessing Game implemented in hardware description and assembly languages, illustrating practical applications in digital systems and microprocessor interfacing.

3to8decoder alu arithmetic-logic-unit assembly carry-look-ahead-adder carry-select-adder counter decoder encoder finite-state-machine guessing-game microcontroller microcontroller-programming pic16f84a system-design systemverilog verilog

Last synced: 11 Apr 2025

https://github.com/komed3/8-bit-alu

Project to build an 8-bit arithmetic logic unit (ALU) consisting only of transistors

8-bit 8-bit-alu arithmetic-logic-unit circuit cpu logic-gates logisim-alu transistor-level

Last synced: 24 Feb 2026

https://github.com/brainiac2677/cse-306-computer-architecture

Contains the project resources of the course CSE306. These were group projects.

arithmetic-logic-unit computer-architecture floating-point-adder mips-architecture

Last synced: 04 Jan 2026

https://github.com/anonto050/cse-306-computer_architecture

Contains codes and designs of computer architecture assignments

arithmetic-logic-unit computer-architecture floating-point-adder mips

Last synced: 31 Jan 2026

https://github.com/bur4kbey/digital-design-4-bit-alu

This project implements a 4-bit ALU with six operations using Verilog on the Tang Nano 9K FPGA. It includes a detailed circuit simulation, real-life construction, and comprehensive documentation for open-source use.

4-bit arithmetic-logic-unit fpga logisim-evolution tangnano9k verilog

Last synced: 02 Feb 2026

https://github.com/sithulaka/8-bit-alu-implementation

This repository demonstrates an 8-bit Arithmetic Logic Unit (ALU) built using IoT components like a Raspberry Pi Pico, seven-segment displays, and SN74LS83N Adder ICs to perform binary addition.

8-bit alu arithmetic-logic-unit binary-addition iot raspberry-pi-pico seven-segment-displays

Last synced: 24 Jul 2025

https://github.com/shahriar-raj/cse_306-computer-architecture-sessional

This repository contains all home and lab assignments for the CSE 306 : Computer Architecture Sessional course, part of our Term-1, Level-3 curriculum. It applies theories from CSE 305 to implement different components of computer architecture..

4-bit-pc arithmetic-logic-unit computer-architecture floating-point-adder

Last synced: 16 Feb 2026

https://github.com/yingjieqiao/comp-struct-2d

16-bit ripple carry adder. ISTD 2D challenge, 50.002 section.

arithmetic-logic-unit

Last synced: 23 Jun 2025

https://github.com/hr-fahim/full-single-cycle-pipelined-datapath-with-control-unit-using-16bit-alu

In a Single Cycle Datapath, each of the Datapath's components carries out an instruction in one cycle. Therefore, no Datapath component may be utilized more than once each cycle.

arithmetic-logic-unit computer-architecture datapath mips-pipeline-processor

Last synced: 07 Feb 2026

https://github.com/barannmeisterr/32-bit-alu-design

This project is a 32-bit Arithmetic Logic Unit (ALU) designed in SystemVerilog as part of a MIPS microprocessor simulation. The ALU supports various arithmetic and logical operations and includes a custom-built 32-bit full adder, one 2-to-1 MUX, one 4-to-1 MUX, one AND gate , one OR gate and the Zero Extend Logic

alu arithmetic-logic-unit computerorganization fulladder inverter logic-gates multiplexer mux systemverilog verilog

Last synced: 13 Feb 2026

https://github.com/ibraam-nashaat/arithmetic-logic-unit

ALU capable of adding, subtracting, multiplying and calculating the remainder of two signed 3-bits numbers.

alu arithmetic-logic-unit arithmetic-units logic-unit

Last synced: 02 Feb 2026