Ecosyste.ms: Awesome

https://github.com/lakshmi-sathi/avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

analog-circuit asic charge-pump clock-multiplier ic intellectual-property manufacturable phase-detector pll rtl2gds

Last synced: 20 Nov 2024