https://github.com/tamoziit/computer-architecture-organisation-lab

Vivado VHDL

2-s-complement adder alu behavioral-modeling comparator dataflow-model encoder-decoder-multiplexer flip-flops logic-gates parity-check ripple-carry-adder rtl-design structural-model subtractor testbench universal-gate vhdl vivado-hls vivado-simulator waveform

Last synced: 18 Feb 2026