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Projects in Awesome Lists by ccelio

A curated list of projects in awesome lists by ccelio .

https://github.com/ccelio/chisel-style-guide

A Style Guide for the Chisel Hardware Construction Language

Last synced: 19 Dec 2024

https://github.com/ccelio/speckle

A wrapper for the SPEC CPU2006 benchmark suite.

Last synced: 27 Oct 2024

https://github.com/ccelio/riscv-boom-doc

Documentation for the BOOM processor

Last synced: 19 Dec 2024

https://github.com/ccelio/riscv-hpmcounters

A simple utility for doing RISC-V HPM perf monitoring.

riscv

Last synced: 27 Oct 2024

https://github.com/ccelio/initramfs_linux_flow

This is a hacky tool for building a BBL+Linux+InitRAMFS image for RISC-V.

Last synced: 27 Oct 2024

https://github.com/ccelio/riscv-pythia

A RISC-V superscalar front-end simulator.

Last synced: 01 Nov 2024

https://github.com/ccelio/coremarkpro-util-make-riscv

The utility files to port CoreMark-Pro to RISC-V.

Last synced: 19 Dec 2024

https://github.com/ccelio/tilecoderaytracer

A simple ray tracer targeting both Tilera's TILE64 and x86 processors.

Last synced: 19 Dec 2024

https://github.com/ccelio/qsub-fpga

Infrastructure for managing FPGA cluster via qsub.

Last synced: 19 Dec 2024

https://github.com/ccelio/isa-analysis-tools

A set of scripts and tools that are helpful for analyzing different ISAs' code behavior.

Last synced: 19 Dec 2024