Projects in Awesome Lists by mpatil
A curated list of projects in awesome lists by mpatil .
https://github.com/mpatil/sv-edsl-poc
Proof of concept of embedding a DSL into SystemVerilog
Last synced: 15 Apr 2025
https://github.com/mpatil/sv-json-schema
This is a SystemVerilog configuration class generation -- from JSON schema -- utility.
generator json-schema systemverilog
Last synced: 20 Feb 2025
https://github.com/mpatil/svacc
System Verilog YACC
parser-generator systemverilog yacc
Last synced: 15 Mar 2025