Projects in Awesome Lists by oddball
A curated list of projects in awesome lists by oddball .
https://github.com/oddball/ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
ip-xact systemverilog verilog vhdl
Last synced: 13 Sep 2025
https://github.com/oddball/embedpythoninverilogexample
embedPythonInVerilogExample
Last synced: 13 Sep 2025
https://github.com/oddball/autodependmakefileexample
autoDependMakefileExample
Last synced: 08 Oct 2025