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Projects in Awesome Lists by risclite

A curated list of projects in awesome lists by risclite .

https://github.com/risclite/SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

Last synced: 09 Nov 2024

https://github.com/risclite/R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

8bit cpu tiny verilog

Last synced: 28 Nov 2024

https://github.com/risclite/ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

32-bit armv4 cpu verilog

Last synced: 28 Nov 2024