Projects in Awesome Lists by riscv-software-src
A curated list of projects in awesome lists by riscv-software-src .
https://github.com/riscv-software-src/riscv-isa-sim
Spike, a RISC-V ISA Simulator
Last synced: 13 May 2025
https://github.com/riscv-software-src/opensbi
RISC-V Open Source Supervisor Binary Interface
Last synced: 14 May 2025
https://github.com/riscv-software-src/riscv-tools
RISC-V Tools (ISA Simulator and Tests)
Last synced: 17 Dec 2025
https://github.com/riscv-software-src/riscv-angel
JavaScript RISC-V ISA Simulator. Boots linux in a web-browser.
Last synced: 07 Apr 2025
https://github.com/riscv-software-src/homebrew-riscv
homebrew (macOS) packages for RISC-V toolchain
Last synced: 05 Apr 2025
https://github.com/riscv-software-src/riscv-perf-model
Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
modeling out-of-order performance-analysis risc-v
Last synced: 04 Apr 2025
https://github.com/riscv-software-src/riscv-config
RISC-V Configuration Validator
Last synced: 28 Feb 2026
https://github.com/riscv-software-src/riscv-unified-db
Machine-readable database of the RISC-V specification, and tools to generate various views
Last synced: 09 Apr 2025
https://github.com/riscv-software-src/riscv-overlay
The Software Overlay TG will specify the requirements for the software overlay feature, both from the FW manager engine and from toolchain aspects, all which will be based on the current RISC-V ISA and extensions.
Last synced: 29 Jul 2025
https://github.com/riscv-software-src/librpmi
Reference implementation of RPMI specification as a library.
Last synced: 20 May 2026
https://github.com/riscv-software-src/riscv-docs-docker
A docker image for building RISC-V documentation
Last synced: 08 Oct 2025
https://github.com/riscv-software-src/sail-riscv-tests
Precompiled test suites for comprehensive testing of the Sail RISC-V model
Last synced: 11 Feb 2026
https://github.com/riscv-software-src/se-sig-analysis
Toolchains, scripts, and workloads to analyze proposed instructions as part of the Scalar Efficiency SIG.
Last synced: 16 Jun 2026
https://github.com/riscv-software-src/riscv-mirror-stf-library
Mirror of STF Library. The acronym STF stands for Simulation Trace Format. This is intended to be used with Sparta-based simulators, but that's not necessary.
Last synced: 08 Sep 2025
https://github.com/riscv-software-src/template-riscv-code
This repository will be cloned for new RISC-V (only) code projects
Last synced: 01 Mar 2026