awesome
A curated list of awesome resources for HDL design and verification
https://github.com/hdl/awesome
Last synced: 5 days ago
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Uncategorized
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Uncategorized
- rajesh-s/computer-engineering-resources
- architecnologia.es/herramientas-electronica
- semiwiki.com: EDA Open Source and Free Tools Wiki
- suarezvictor/suarezvictor.github.io: storeroom/README.md
- vhdl/awesome-vhdl
- drom/awesome-hdl
- fukatani/awesome-hdl
- ben-marshall/awesome-open-hardware-verification
- kelu124/awesome-latticeFPGAs
- pkuzjx/eda-collection
- Nic30/hdlConvertor#similar-projects
- Nic30/hwt#similar-projects
- Nic30/hwtLib#repositories-with-opensource-hw
- HardwareIR/netlistDB#similar-libraries
- rajesh-s/computer-engineering-resources
- aolofsson/awesome-hardware-tools
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Categories
Sub Categories
Keywords
vhdl
6
verilog
5
awesome
4
fpga
4
awesome-list
3
rtl
2
python
2
systemverilog
2
verification
1
hardware
1
formal-verification
1
coverage
1
constrained-random-verification
1
hdl
1
hardware-description-language
1
vhdl-library
1
vhdl-ip-core
1
vhdl-collection
1
hardware-designs
1
uvm
1
systemc
1
simulator
1
hls
1
hcl
1
compiler
1
codegenerator
1
codegen
1
vhdl-parser
1
verilog-parser
1
systemverilog-parser
1
parser
1
antrl4
1
lattice-fpga
1
icestorm
1
collection
1