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Projects in Awesome Lists by gmbeddard

A curated list of projects in awesome lists by gmbeddard .

https://github.com/gmbeddard/ee201-funds-comp-engineering-risc5cpuproject

A step-by-step implementation of a RISC-V CPU using SystemVerilog, including modules for ALU operations, memory instructions, and branching. Features testbenches, assembler integration, and optional FPGA deployment for real-world testing. Perfect for exploring CPU architecture and hardware design.

assembly-language computer-engineering cpu risc-v systemverilog

Last synced: 13 Jan 2025

https://github.com/gmbeddard/ee200-binary_tree_tests

A comprehensive test suite for evaluating 10 BST implementations. Includes validation of insertion, deletion, search, traversal, and memory management, with detailed analysis of failures and bugs.

binary-search-tree cpp20 unit-testing

Last synced: 12 Jan 2025

https://github.com/gmbeddard/ee200-templated_priority_queue

An efficient implementation of a PriorityQueue class with a custom max-heap. Supports dynamic operations like insertion, removal, and retrieval of the highest-priority element, ensuring robust and flexible performance.

cpp20 datastructures dynamicmemorymanagement memory-management priority-queue

Last synced: 12 Jan 2025