https://github.com/secworks/aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

aes asic block-cipher encryption fpga

Last synced: 01 Feb 2026

https://github.com/secworks/sha256

Hardware implementation of the SHA-256 cryptographic hash function

Last synced: 11 Jan 2026

https://github.com/secworks/sha1

Verilog implementation of the SHA-1 cryptgraphic hash function

Last synced: 01 Feb 2026

https://github.com/secworks/sha512

Verilog implementation of the SHA-512 hash function.

Last synced: 01 Feb 2026

https://github.com/secworks/blake2

Hardware implementation of the blake2 hash function

Last synced: 14 Mar 2026

https://github.com/secworks/blake2s

Verilog implementation of the 32-bit version of the Blake2 hash function

Last synced: 01 Feb 2026

https://github.com/secworks/prince

The Prince lightweight block cipher in Verilog.

Last synced: 01 Feb 2026

https://github.com/secworks/poly1305

Hardware implementation of the poly1305 message authentication function.

Last synced: 01 Feb 2026

https://github.com/secworks/verilator_template

(Hopefully) simple template for a Verilator SystemVerilog project with a usable testbench

Last synced: 01 Feb 2026

https://github.com/secworks/md5

Hardware implementation of the hash function md5

Last synced: 01 Feb 2026