https://github.com/sofiavalos/verilog_ethernet_10g_pcs

Bloques y bancos de pruebas PCS para Ethernet 10G.

ethernet pcs verilog

Last synced: 19 Mar 2026

https://github.com/sofiavalos/signal-generators-and-checkers-for-ethernet

Last synced: 01 Mar 2026

https://github.com/sofiavalos/proyecto-final

Proyecto final Arg Programa

Last synced: 30 Jul 2025

https://github.com/sofiavalos/verilog_ethernet_10g_mac

Bloques y bancos de pruebas MAC para Ethernet 10G.

ethernet mac verilog

Last synced: 30 Mar 2025

https://github.com/sofiavalos/portafolio-front-end

Last synced: 02 Sep 2025

https://github.com/sofiavalos/lfsr

Bloques y bancos de pruebas para un LFSR de 8 bits.

Last synced: 26 Feb 2026

https://github.com/sofiavalos/electronicadigital3

Last synced: 17 Jul 2025

https://github.com/sofiavalos/ethernet_10g_documentation_web

Documentación de bloques MAC y PCS para Ethernet-10GBASE

Last synced: 19 Mar 2026