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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
- GitHub: https://github.com/topics/riscv
- Wikipedia: https://en.wikipedia.org/wiki/riscv
- Aliases: risc-v, riscv-cpu, riscv-core,
- Last updated: 2024-12-18 00:26:47 UTC
- JSON Representation
https://github.com/cosecseccot/riscv32i-assembler
A custom Assembler for RISCV32I ISA
assembler assembly assembly-language risc-v riscv riscv32
Last synced: 17 Nov 2024
https://github.com/rvangelse/risc-v
Ejercicios de practica implementados en RISC-V
arrays bit bitmanipulation iteration recursion recursive risc-v riscv riscv32
Last synced: 15 Nov 2024
https://github.com/steliospapamichail/risc-v-projects
Various programs written in Assembly for RISC-V CPUs
assembly risc-v riscv x86 x86-assembly
Last synced: 13 Nov 2024
https://github.com/rinhizakura/amirvos
Write an mini RISC-V operating system with Rust, just for fun!
operating-system riscv riscv64 rust
Last synced: 07 Nov 2024
https://github.com/trmckay/docker-rust-riscv
Rust, GNU, and QEMU toolchains for riscv64 and riscv32
Last synced: 17 Nov 2024
https://github.com/m3y54m/pcb-esp-c3-13-breakout-board
ESP-C3-13 Breakout Board
altium ble bluetooth breakout-board esp32 esp32-c3 pcb riscv wifi
Last synced: 20 Nov 2024
https://github.com/bakaq/rust-riscv-os
A Rust RISC-V OS to learn embedded programming.
operating-system os risc-v riscv riscv64 rust
Last synced: 17 Nov 2024
https://github.com/skpro-glitch/shorthand-risc
This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai
assembler assembly assembly-language assembly-language-programming compiler compiler-construction compiler-design compiler-optimization compiler-principles compilers risc risc-processor risc-v riscv shorthand shorthand-notation shorthand-syntax
Last synced: 21 Nov 2024
https://github.com/nuclei-software/nuclei-tool-guide
Nuclei Tools(IDE/Toolchain/Qemu/OpenOCD/Xlmodel) Guide
documentation nuclei riscv tools
Last synced: 01 Dec 2024
https://github.com/penberg/riscv-rs
Yet another RISC-V emulator written in Rust.
Last synced: 25 Nov 2024
https://github.com/werifu/rcorecompdaily2022
Daily Schedule for rCore Comp 2022 https://github.com/LearningOS/rust-based-os-comp2022
Last synced: 08 Dec 2024
https://github.com/xigh/libriscv-rs
RISCV decoder / encoder library written in Rust
risc-v riscv riscv-asm riscv-assembly rust
Last synced: 10 Nov 2024
https://github.com/candrewlee14/xv6-riscv-zig
xv6-riscv + Zig
operating-systems riscv xv6 xv6-riscv zig
Last synced: 08 Nov 2024
https://github.com/nyh-workshop/esp32s3-ulp-riscv-hello
This is a simple ESP32S3 ULP RiscV Blink example.
Last synced: 21 Dec 2024
https://github.com/shuregg/riscv-simple-cpu
Creating a risc-v processor
cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl
Last synced: 13 Dec 2024
https://github.com/64kramsystem/parsec-riscv-performance-testing
Program for setting up and running the PARSEC suite on an emulated RISC-V environment, used for my coauthored research paper.
bash emulation parsec-benchmark performance qemu riscv shell-script
Last synced: 18 Dec 2024
https://github.com/3-o-3/riscv-zxbt-extension
RISC-V Blanced Ternary ISA Extension
instruction-set-architecture risc-v riscv ternary ternary-computer
Last synced: 18 Dec 2024
