https://github.com/3-o-3/riscv-zxbt-extension

RISC-V Blanced Ternary ISA Extension

instruction-set-architecture risc-v riscv ternary ternary-computer

Last synced: 18 Dec 2024

https://github.com/kivikakk/sae

RV32I softcore

amaranth fpga riscv

Last synced: 16 Dec 2024

https://github.com/sergz72/riscv

RISCV CPU Projects

ch32v ch32v203 riscv usb-cdc

Last synced: 07 Dec 2024

https://github.com/eveheeero/book

architecture arm arm64 assembly cpu document mips mips32 mips64 riscv x64 x86 x86-64

Last synced: 17 Nov 2024

https://github.com/lupyuen/nuttx-mmu-log-parser

Parser for MMU Logs generated by Apache NuttX RTOS

bl808 nuttx ox64 qemu riscv riscv64

Last synced: 14 Nov 2024

https://github.com/xigh/libriscv-rs

RISCV decoder / encoder library written in Rust

risc-v riscv riscv-asm riscv-assembly rust

Last synced: 10 Nov 2024

https://github.com/ralphhightower/rh

@RalphHightower — Website

arm64 beer canon csharp digital-photography dotnet dslr-camera film-photography linux photography risc-v riscv single-board-computers slr-camera software-development software-engineering solaris university-of-south-carolina unix windows

Last synced: 16 Dec 2024

https://github.com/calint/tang-nano-20k--riscv

riscv rv32i tang-nano-20k verilog

Last synced: 11 Nov 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 06 Nov 2024

https://github.com/muhammadtalhasami/riscv-assembly

This repo is the learning journey of the riscv assembly language. you will learn how to write the high level code in to the riscv assembly code.

high-level-language riscv riscv-assembly riscv-assembly-language riscv32 riscv64 spike spike-simulator venus venus-simulator venus-simulator-riscv

Last synced: 06 Nov 2024

https://github.com/bakaq/rust-riscv-os

A Rust RISC-V OS to learn embedded programming.

operating-system os risc-v riscv riscv64 rust

Last synced: 17 Nov 2024

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/trmckay/docker-rust-riscv

Rust, GNU, and QEMU toolchains for riscv64 and riscv32

docker riscv rust

Last synced: 17 Nov 2024

https://github.com/candrewlee14/xv6-riscv-zig

xv6-riscv + Zig

operating-systems riscv xv6 xv6-riscv zig

Last synced: 08 Nov 2024

https://github.com/steliospapamichail/risc-v-projects

Various programs written in Assembly for RISC-V CPUs

assembly risc-v riscv x86 x86-assembly

Last synced: 13 Nov 2024

https://github.com/rvangelse/risc-v

Ejercicios de practica implementados en RISC-V

arrays bit bitmanipulation iteration recursion recursive risc-v riscv riscv32

Last synced: 15 Nov 2024

https://github.com/werifu/rcorecompdaily2022

Daily Schedule for rCore Comp 2022 https://github.com/LearningOS/rust-based-os-comp2022

os riscv rust

Last synced: 08 Dec 2024

https://github.com/rinhizakura/amirvos

Write an mini RISC-V operating system with Rust, just for fun!

operating-system riscv riscv64 rust

Last synced: 07 Nov 2024

https://github.com/penberg/riscv-rs

Yet another RISC-V emulator written in Rust.

riscv riscv-emulator rust

Last synced: 25 Nov 2024

https://github.com/nyh-workshop/esp32s3-ulp-riscv-hello

This is a simple ESP32S3 ULP RiscV Blink example.

esp-idf esp32s3 riscv ulp

Last synced: 21 Dec 2024

https://github.com/bluebrown/riscv-examples

riscv examples

assembly c embedded kernel osdev qemu riscv riscv64 rust zig

Last synced: 14 Dec 2024

https://github.com/jaxvanyang/riscv-opcodes

RISC-V opcode data for easy parsing.

riscv riscv32 riscv64

Last synced: 30 Nov 2024

https://github.com/jlkiri/pathos

A simple OS that runs on the RISC-V architecture.

os riscv rust

Last synced: 06 Dec 2024