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RISC-V

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

GitHub: https://github.com/topics/riscv
Wikipedia: https://en.wikipedia.org/wiki/riscv
Aliases: risc-v, riscv-cpu, riscv-core,
Last updated: 2024-12-18 00:26:47 UTC
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https://github.com/nyh-workshop/esp32s3-ulp-riscv-hello

This is a simple ESP32S3 ULP RiscV Blink example.

esp-idf esp32s3 riscv ulp

Last synced: 21 Dec 2024

https://github.com/64kramsystem/parsec-riscv-performance-testing

Program for setting up and running the PARSEC suite on an emulated RISC-V environment, used for my coauthored research paper.

bash emulation parsec-benchmark performance qemu riscv shell-script

Last synced: 18 Dec 2024

https://github.com/penberg/riscv-rs

Yet another RISC-V emulator written in Rust.

riscv riscv-emulator rust

Last synced: 25 Nov 2024

https://github.com/shiritai/aias-lab6-spring-2024

Lab6 of AI computing Architecture and System (2024 spring) around riscv emulator and implementation of fibonacci, sudoku (2x2) and maxpool in RISC-V

assembly fibonacci maxpool2d riscv riscv-emulator sudoku

Last synced: 08 Nov 2024

https://github.com/eveheeero/book

architecture arm arm64 assembly cpu document mips mips32 mips64 riscv x64 x86 x86-64

Last synced: 17 Nov 2024

https://github.com/jaxvanyang/riscv-opcodes

RISC-V opcode data for easy parsing.

riscv riscv32 riscv64

Last synced: 30 Nov 2024

https://github.com/rinhizakura/amirvos

Write an mini RISC-V operating system with Rust, just for fun!

operating-system riscv riscv64 rust

Last synced: 07 Nov 2024

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/cosecseccot/riscv32i-assembler

A custom Assembler for RISCV32I ISA

assembler assembly assembly-language risc-v riscv riscv32

Last synced: 17 Nov 2024

https://github.com/muhammadtalhasami/riscv-assembly

This repo is the learning journey of the riscv assembly language. you will learn how to write the high level code in to the riscv assembly code.

high-level-language riscv riscv-assembly riscv-assembly-language riscv32 riscv64 spike spike-simulator venus venus-simulator venus-simulator-riscv

Last synced: 06 Nov 2024

https://github.com/steliospapamichail/risc-v-projects

Various programs written in Assembly for RISC-V CPUs

assembly risc-v riscv x86 x86-assembly

Last synced: 13 Nov 2024

https://github.com/the-pinbo/risc-spm

This project involves the development and enhancement of a RISC Stored-Program Machine (RISC SPM), based on the architecture detailed in "Advanced Digital Design with the Verilog HDL" by Michael D. Ciletti.

computer-architecture riscv verilog

Last synced: 06 Nov 2024