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https://github.com/TM90/awesome-hwd-tools

A curated list of awesome open source hardware design tools
https://github.com/TM90/awesome-hwd-tools

List: awesome-hwd-tools

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A curated list of awesome open source hardware design tools

Awesome Lists containing this project

README 

        
# awesome-hwd-tools

A curated list of awesome open source hardware design tools with a focus on chip design.



For electronic hardware tools without a focus on chip design see:



https://github.com/kitspace/awesome-electronics



Inspired by [awesome-python](https://github.com/vinta/awesome-python).



## Semi Custom Design/ FPGAs



[Nic30/hdlConverter](https://github.com/Nic30/hdlConvertor) - Python System-Verilog/VHDL Parser



[christiklein/simpy](https://gitlab.com/team-simpy/simpy) - discrite event based simulation framework



[chipmuenk/pyFDA](https://github.com/chipmuenk/pyFDA) - A python tool to design time discrete filters



[efabless/openlane](https://github.com/efabless/openlane) - Automated RTL to GDS flow based on openRoad, Yosys and more...



[ahmed-agiza/EDAViewer](https://github.com/ahmed-agiza/EDAViewer) - EDAV is a cloud-based open-source viewer for electronic design automation (EDA) design files (LEF, DEF)



### Modelling



[cornell-brg/pymtl3](https://github.com/cornell-brg/pymtl3) - hardware modeling framework



[mortbopet/VSRTL](https://github.com/mortbopet/VSRTL) - Visual Simulation of Register Transfer Logic



### Hardware Description Languages



[freechipsproject/Chisel](https://github.com/freechipsproject/chisel3/) - Hardware Description Language embedded in Scala developed at UC Berkeley



[phanrahan/Magma](https://github.com/phanrahan/magma) - A Hardware Description Language embedded in Python



[llvm/circt](https://github.com/llvm/circt) - Intermediate representation for rtl (used by Chisel)



[myhdl/MyHDL](https://github.com/myhdl/myhdl) - Python as a Hardware Description and Verification Language



[clash-lang/clash-compiler](https://github.com/clash-lang/clash-compiler) - A Hardware Description Language written and inspired by Haskell



A much more detailed and specific list for hardware description languages can be found at [drom/awesome-hdl](https://github.com/drom/awesome-hdl).



### Wave Viewers



[gtkwave](http://gtkwave.sourceforge.net/) - GTK based waveform viewer



[wavedrom/wavedrom](https://github.com/wavedrom/wavedrom) - Timing Diagrams in Java Script



### Simulation



[steveicarus/iverilog](https://github.com/steveicarus/iverilog) - Icarus Verilog Simulator



[ghdl/ghdl](https://github.com/ghdl/ghdl) - VHDL Simulator



### Synthesis



[YosysHQ/yosys](https://github.com/YosysHQ/yosys) - Synthesis Flow



### Timing Analysis



[abk-openroad/OpenSTA](https://github.com/abk-openroad/OpenSTA) - static timing analysis



[OpenTimer/OpenTimer](https://github.com/OpenTimer/OpenTimer) - timing analysis tool for vlsi systems



### Verification



[YosysHQ/SymbiYosys](https://github.com/YosysHQ/SymbiYosys) - formal verification flow and tool



[cocotb/cocotb](https://github.com/cocotb/cocotb) - Creating Verilog/VHDL testbenches with python 



## Open Source PDK



[leviathanch/libresiliconprocess](https://github.com/leviathanch/libresiliconprocess) - A 1um open process specification



[google/skywater-pdk](https://github.com/google/skywater-pdk) - Open Source Process SkyWater 130nm



## Full Custom Design



[heitzmann/gdspy](https://github.com/heitzmann/gdspy) - manipulating GDSII files in Python



[unihd-cag/skillbridge](https://github.com/unihd-cag/skillbridge) - A seamless python to Cadence Virtuoso Skill interface



[electronics-and-drives/SPAM](https://github.com/electronics-and-drives/SPAM) - SPAM is a package management system for Cadence SKILL



[electronics-and-drives/ml2tikz](https://github.com/electronics-and-drives/ml2tikz) - Virtuoso layout to tikzpicture



[MatthewLoveQUB/SKILL_Tools](https://github.com/MatthewLoveQUB/SKILL_Tools) - Skill++ Tools including a test framework



[EDDRSoftware/oaFileParser](https://github.com/EDDRSoftware/oaFileParser) - oaFile Parser



[scikit-rf/scikit-rf](https://github.com/scikit-rf/scikit-rf) - RF and Microwave Design in scikit



[mph-/lcapy](https://github.com/mph-/lcapy) - Lcapy is a Python package for linear circuit analysis. It uses SymPy for symbolic mathematics.



[YosysHQ/PADRING](https://github.com/YosysHQ/padring) - A padring generator for asics



[DegateCommunity/Degate](https://github.com/DegateCommunity/Degate) - Tool for VLSI reverse engineering



[cap1tan/wafermap](https://github.com/cap1tan/wafermap) - A python package to plot maps of semiconductor wafers



### Layout Generation/ Manipulation



[ucb-art/BAG_framework](https://github.com/ucb-art/BAG_framework) - Berkeley Analog Generator



[VLSIDA/OpenRAM](https://github.com/VLSIDA/OpenRAM) - open-source SRAM Compiler



[KLayout/klayout](https://github.com/KLayout/klayout) - scriptable Layout Viewer and Editor



### Simulation



[ngspice](http://ngspice.sourceforge.net/index.html) - Spice Simulator



[FabriceSalvaire/pyspice](https://github.com/FabriceSalvaire/PySpice) - Simulating and creating Spice Circuits with Python



### Mixed Signal Design 



[Isotel/mixedsim](https://github.com/Isotel/mixedsim) - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice



## Documentation



[SchemDraw](https://bitbucket.org/cdelker/schemdraw/src/master/) - producing circuit diagrams with python