An open API service indexing awesome lists of open source software.

Projects in Awesome Lists tagged with sequential-logic

A curated list of projects in awesome lists tagged with sequential-logic .

https://github.com/mcquerol/vhdl-projects

VHDL projects for combinational and sequential logic design on FPGA.

combinational-logic flip-flops latches logisim memory sequential-logic vhdl

Last synced: 19 Mar 2026

https://github.com/z1skgr/calculatorvhdl

Design of the implementation of a calculator connected on the integrated FPGA

calculator combinational-logic fpga sequential-logic stack vhdl xilinx-ise

Last synced: 19 Mar 2026

https://github.com/georgescoding/traffic-lights

Traffic light system for a four way intersection simulated using a Moore state machine and displayed on a FPGA

fpga-board sequential-logic state-machine traffic-light vhdl-coursework

Last synced: 06 Mar 2026

https://github.com/aathish04/asciimorsecircuit

This repository contains the project files and report for an ASCII letter to Morse Code converter built using only basic sequential and combinational logic circuits.

ascii combinational-logic logisim-evolution morse-code sequential-logic

Last synced: 28 Jan 2026

https://github.com/ravigohel/all-bitcoin-keys

A high-performance Python Flask application that generates Bitcoin private keys sequentially and displays their corresponding addresses with real-time balance information. This is a complete conversion of the original Angular TypeScript application with enhanced features and optimizations.

bitcoin private-key sequential-logic

Last synced: 06 Oct 2025

https://github.com/ewdlop/verilog-notes

HDLBit-Pratice. https://hdlbits.01xz.net/wiki/Main_Page

combinational-logic finte-state-machine flip-flops sequential-logic verilog

Last synced: 03 Nov 2025

https://github.com/octokerbs/fcen-organizaciondelcomputador-1

Sequential logic - Instruction set architecture - Micro programming - Input/Output - Analog/Digital and Digital/Analog conversion - Memory bus

cache circuits-simulator isa risc-v sequential-logic

Last synced: 11 Mar 2025

https://github.com/octokerbs/FCEN-OrganizacionDelComputador-1

Sequential logic - Instruction set architecture - Micro programming - Input/Output - Analog/Digital and Digital/Analog conversion - Memory bus

cache circuits-simulator isa risc-v sequential-logic

Last synced: 02 Nov 2025