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Projects in Awesome Lists by birdybro

A curated list of projects in awesome lists by birdybro .

https://github.com/birdybro/pdp2011_mister

Port of sytse's PDP2011 core to the MiSTer FPGA Platform

Last synced: 05 Dec 2024

https://github.com/birdybro/tms34010_docs

Some documentation on the Texas Instruments 34010 Graphics Processor (aka TMS34010) for reference

Last synced: 05 Dec 2024

https://github.com/birdybro/psx2x_mister

fork of Robert's repo with updates hopefully

Last synced: 05 Dec 2024

https://github.com/birdybro/pc6001_mister

Port of a PC-6001 core to MiSTer FPGA

Last synced: 05 Dec 2024

https://github.com/birdybro/rgb_conv_verilog

different rgb colorspace conversion techniques from rgb_xxx to rgb_888

Last synced: 05 Dec 2024

https://github.com/birdybro/partyparrot_mister

Party Parrot FPGA core by kingyoPiyo ported to MiSTer by birdybro

Last synced: 03 Dec 2024

https://github.com/birdybro/biosdb_mister

Bios DB for the MiSTer Downloader

Last synced: 03 Dec 2024

https://github.com/birdybro/vgm-guide

a guide to logging and manipulating Genesis/Mega Drive VGM files

Last synced: 05 Dec 2024

https://github.com/birdybro/pocketstation_mister

Pocketstation core for MiSTer

Last synced: 05 Dec 2024

https://github.com/birdybro/rpt_mister

compilation of compilation reports of MiSTer cores

Last synced: 05 Dec 2024

https://github.com/birdybro/mister_helpz

Just some random stuff so I can help people better

Last synced: 05 Dec 2024

https://github.com/birdybro/pc8001m_mister

port of PC8001M (by radiojunkbox) to MiSTer

Last synced: 05 Dec 2024

https://github.com/birdybro/siege-es2e3

A simple game built for the Nexys A7 FPGA board in Verilog. Built on top of a custom VGA driver.

Last synced: 05 Dec 2024

https://github.com/birdybro/birdybrodb_mister

just my personal db of MiSTer FPGA configs and stuff so I can sync between my three MiSTer's and reinstall easier

Last synced: 05 Dec 2024

https://github.com/birdybro/mister.ini_mister

A compilation of MiSTer.ini configuration examples for MiSTer FPGA

Last synced: 05 Dec 2024

https://github.com/birdybro/ti83p_mister

TI-83 Plus calculator VHDL implementation by hellux ported to the MiSTer FPGA platform

Last synced: 05 Dec 2024

https://github.com/birdybro/birdybro.github.io

just a blog or something

Last synced: 05 Dec 2024

https://github.com/birdybro/slugcross_mister

Slug Cross for MiSTer FPGA

Last synced: 05 Dec 2024

https://github.com/birdybro/arcade-turkeyshoot_mister_old

Turkey Shoot by darfpga ported to MiSTer

Last synced: 05 Dec 2024

https://github.com/birdybro/fir_filter_sv

Work in progress FIR Filter written in SystemVerilog

Last synced: 05 Dec 2024

https://github.com/birdybro/the_pile

just a pile of random stuff I mess with

Last synced: 05 Dec 2024

https://github.com/birdybro/chatgpt4_sv

some goofy ai built systemverilog modules, none of these probably work properly, just for fun

Last synced: 05 Dec 2024

https://github.com/birdybro/screenshot_mister

Exploring the possibility of a screenshot viewing core to simulate a paused screen for analysis

Last synced: 05 Dec 2024

https://github.com/birdybro/test_pattern_yc

MiSTerFPGA - Test Pattern

Last synced: 05 Dec 2024

https://github.com/birdybro/blogtest

birdybro blog or somethin

Last synced: 05 Dec 2024

https://github.com/birdybro/rgbs2ypbpr_mister

Just a fun simple external adapter so you don't have to mod your AG620x-based HDMI to VGA Direct video Adapter for YPbPr

Last synced: 05 Dec 2024

https://github.com/birdybro/mister_jsondb

Just some json DB files for Downloader use.

Last synced: 05 Dec 2024

https://github.com/birdybro/birdybro_configs

Just some of my personal configurations for the MiSTer. Making public for the heck of it.

Last synced: 05 Dec 2024

https://github.com/birdybro/alphamission

Alpha Mission and clones FPGA core for MiSTer

Last synced: 05 Dec 2024

https://github.com/birdybro/mister-barcade

A 3d Printed Bartop Arcade design project modified for use with the MiSTer FPGA

Last synced: 05 Dec 2024

https://github.com/birdybro/birdybro

Last synced: 05 Dec 2024

https://github.com/birdybro/nand2tetris_mister

Nand2Tetris for MiSTer (as a learning experience for me).

hdl mister misterfpga tetris verilog verilog-hdl

Last synced: 05 Dec 2024

https://github.com/birdybro/cegen_sv

Simple synchronous 50% duty cycle clock generator with external division factor parameter, written in SystemVerilog

Last synced: 05 Dec 2024