Projects in Awesome Lists tagged with timing-analysis
A curated list of projects in awesome lists tagged with timing-analysis .
https://github.com/The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 11 May 2025
https://github.com/the-openroad-project/openroad
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
cpp def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 14 May 2025
https://github.com/rokath/trice
🟢 super fast 🚀 tiny 🐥 𝘾 printf-look-and-feel ✍ trace code, in ⚡ interrupts ⚡ too ‼️, and real-time PC 💻 logging 👀
c compression data-recording debugging diagnostics embedded encryption golang instrumentation logging monitoring multi-language-support printf real-time rtos serial time-measurement timing-analysis tool trace
Last synced: 12 Jan 2026
https://github.com/the-openroad-project/openroad-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 22 Feb 2026
https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
def eda gdsii lef opendb-database openroad rtl tcl timing-analysis verilog
Last synced: 22 Jul 2025
https://github.com/LukasHedegaard/pytorch-benchmark
Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption
benchmark deep-learning flops gpu jetson python pytorch timing-analysis
Last synced: 22 Jul 2025
https://github.com/lukashedegaard/pytorch-benchmark
Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption
benchmark deep-learning flops gpu jetson python pytorch timing-analysis
Last synced: 08 Oct 2025
https://github.com/zslwyuan/AMF-Placer
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
fpga mixed-size placement placer timing timing-analysis timing-driven
Last synced: 11 May 2025
https://github.com/cgobat/pulsar-nulling
Analysis of radio pulsar parameters and their relationships with nulling statistics
astrophysics catalogs pulsars timing-analysis
Last synced: 21 May 2026
https://github.com/compcode1/nmap-automation
This project automates Nmap scans at scheduled intervals to analyze network activity over time.
automation cybersecurity nmap python scripts timing-analysis
Last synced: 10 Jun 2025
https://github.com/carv-ics-forth/forma
foRMA is a python-based scripted tool that uses SST Dumpi traces to derive a profile of timing, data transfers, data transfer volume etc., for MPI RMA operations.
mpi-rma profiling timing-analysis trace-analysis
Last synced: 29 May 2026
https://github.com/rpigor/tpsim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
eda power-analysis simulator timing-analysis verilog
Last synced: 28 Jun 2025
https://github.com/yasnakateb/multiclocksynchronization
⏰ Fpga Multi Clock Synchronization
cdc clock clock-generator clock-management clock-synchronization digital-design fpga hardware-design mmcm multi-clock producer-consumer systemverilog timing-analysis
Last synced: 26 Feb 2026
https://github.com/yasnakateb/adaptiveclockmanagement
⏳ Adaptive Clock Management in FPGAs Using Binary Search
adaptive-systems binary-search clock clock-divider clock-management digital-design fpga fsm hardware-design systemverilog timing-analysis
Last synced: 28 Feb 2026