awesome-fpga

A collection of some awesome public FPGA projects.
https://github.com/coderonion/awesome-fpga

Last synced: 4 days ago
JSON representation

Blogs
Learning Resources
- WangXuan95/UniPlug-FPGA - FPGA?style=social"/> : 体积小、低成本、易用、扩展性强的 FPGA 核心板。
- sipeed/TangPrimer-20K-example - 20K-example?style=social"/> : AIoT opensource hardware platform. TangPrimer-20K-example project.
- WangXuan95/ZedBoard-Tutorial - Tutorial?style=social"/> : Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard.
- sipeed/TangPrimer-20K-example - 20K-example?style=social"/> : AIoT opensource hardware platform. TangPrimer-20K-example project.
- BrunoLevy/learn-fpga - fpga?style=social"/> : About Learning FPGA, yosys, nextpnr, and RISC-V
- WangXuan95/ZedBoard-Tutorial - Tutorial?style=social"/> : Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard.
- WangXuan95/UniPlug-FPGA - FPGA?style=social"/> : 体积小、低成本、易用、扩展性强的 FPGA 核心板。
Frameworks
- LiteX - digital/litex?style=social"/> : The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create[full FPGA based systems](https://github.com/enjoy-digital/litex/wiki/Projects).
- Chisel - lang.org/](www.chisel-lang.org/)
- SpinalHDL
- VHDL-LS/rust_hdl - LS/rust_hdl?style=social"/> : This repository contains a fast VHDL language server and analysis library written in Rust.
- yupferris/kaze
- dalance/svls
- vivekmalneedi/veridian
- zachjs/sv2v
- nMigen - lang/amaranth?style=social"/> : A modern hardware definition language and toolchain based on Python.
- Migen - labs/migen?style=social"/> : A Python toolbox for building complex digital hardware.
- MyHDL - source package for using Python as a hardware description and verification language.
- PyRTL - transfer level design, simulation, tracing, and testing suitable for teaching and research.
- Veriloggen - Paradigm Hardware Construction Framework.
- HWT
- HDL21 - fritchman/Hdl21?style=social"/> : Analog Hardware Description Library in Python.
- LiteX - digital/litex?style=social"/> : The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create[full FPGA based systems](https://github.com/enjoy-digital/litex/wiki/Projects).
- SpinalHDL
- RustHDL - hdl?style=social"/> : A framework for writing FPGA firmware using the Rust Programming Language.
- VHDL-LS/rust_hdl - LS/rust_hdl?style=social"/> : This repository contains a fast VHDL language server and analysis library written in Rust.
- yupferris/kaze
- dalance/sv-parser - parser?style=social"/> : SystemVerilog parser library fully compliant with IEEE 1800-2017.
- dalance/svls
- dalance/svlint
- vivekmalneedi/veridian
- zachjs/sv2v
- nMigen - lang/amaranth?style=social"/> : A modern hardware definition language and toolchain based on Python.
- Migen - labs/migen?style=social"/> : A Python toolbox for building complex digital hardware.
- MyHDL - source package for using Python as a hardware description and verification language.
- PyRTL - transfer level design, simulation, tracing, and testing suitable for teaching and research.
- Veriloggen - Paradigm Hardware Construction Framework.
- HWT
- HDL21 - fritchman/Hdl21?style=social"/> : Analog Hardware Description Library in Python.
Applications
- Rocket Chip - chip?style=social"/> : Rocket Chip Generator 🚀. This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core.
- FPGAwars/FLIX-V - V?style=social"/> : FLIX-V: FPGA, Linux and RISC-V.
- Ventus(承影) - DSP-LAB/ventus-gpgpu?style=social"/> : Ventus(承影) GPGPU. GPGPU processor supporting RISCV-V extension, developed with [Chisel](https://github.com/chipsalliance/chisel) HDL.
- jbush001/NyuziProcessor
- BrianHGinc/BrianHG-DDR3-Controller - DDR3-Controller?style=social"/> : DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
- alexforencich/verilog-ethernet - ethernet?style=social"/> : Verilog Ethernet components for FPGA implementation.
- openwifi - sdr/openwifi?style=social"/> : open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software.
- ZipCPU/wbuart32
- WangXuan95/Verilog-UART - UART?style=social"/> : 3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。
- XiangShan (香山) - source high-performance RISC-V processor project. "Towards Developing High Performance RISC-V Processors Using Agile Methodology". (**[MICRO 2022](https://ieeexplore.ieee.org/abstract/document/9923860/)**)
- Rocket Chip - chip?style=social"/> : Rocket Chip Generator 🚀. This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core.
- MoonbaseOtago/vroom - V CPU. A new high-end RISC-V implementation.
- SpinalHDL/VexRiscv
- DarkRISCV - V cpu core implemented in Verilog from scratch in one night!
- stnolting/neorv32 - V Processor. 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
- ZipCPU/zipcpu - weight, RISC CPU.
- olofk/serv - The SErial RISC-V CPU.
- riscv-mcu/e203_hbirdv2 - mcu/e203_hbirdv2?style=social"/> : The Ultra-Low Power RISC-V Core. [doc.nucleisys.com/hbirdv2](https://doc.nucleisys.com/hbirdv2/)
- ultraembedded/riscv - V CPU Core (RV32IM).
- ultraembedded/biriscv - bit Superscalar RISC-V CPU.
- WangXuan95/USTC-RVSoC - based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
- enjoy-digital/litepcie - digital/litepcie?style=social"/> : LitePCIe provides a small footprint and configurable PCIe core.
- alexforencich/verilog-pcie - pcie?style=social"/> : Verilog PCI Express Components Readme.
- Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial - Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial?style=social"/> : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
- ultraembedded/core_ddr3_controller
- adibis/DDR2_Controller
- someone755/ddr3-controller - controller?style=social"/> : A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs.
- openwifi - sdr/openwifi?style=social"/> : open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software.
- alexforencich/verilog-ethernet - ethernet?style=social"/> : Verilog Ethernet components for FPGA implementation.
- ZipCPU/wbuart32
- WangXuan95/Verilog-UART - UART?style=social"/> : 3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。
- MoonbaseOtago/vroom - V CPU. A new high-end RISC-V implementation.
- SpinalHDL/VexRiscv
- DarkRISCV - V cpu core implemented in Verilog from scratch in one night!
- stnolting/neorv32 - V Processor. 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
- ZipCPU/zipcpu - weight, RISC CPU.
- olofk/serv - The SErial RISC-V CPU.
- WangXuan95/USTC-RVSoC - based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
- Ventus(承影) - DSP-LAB/ventus-gpgpu?style=social"/> : Ventus(承影) GPGPU. GPGPU processor supporting RISCV-V extension, developed with [Chisel](https://github.com/chipsalliance/chisel) HDL.
- jbush001/NyuziProcessor
- lnis-uofu/OpenFPGA - uofu/OpenFPGA?style=social"/> : The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. [openfpga.readthedocs.io/en/master/](openfpga.readthedocs.io/en/master/). "OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs". (**[IEEE Micro, 2020](https://ieeexplore.ieee.org/abstract/document/9098028/)**)
- Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial - Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial?style=social"/> : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
- enjoy-digital/litepcie - digital/litepcie?style=social"/> : LitePCIe provides a small footprint and configurable PCIe core.
- alexforencich/verilog-pcie - pcie?style=social"/> : Verilog PCI Express Components Readme.
- ultraembedded/core_ddr3_controller
- WangXuan95/FPGA-DDR-SDRAM - DDR-SDRAM?style=social"/> : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
- adibis/DDR2_Controller
- lnis-uofu/OpenFPGA - uofu/OpenFPGA?style=social"/> : The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. [openfpga.readthedocs.io/en/master/](openfpga.readthedocs.io/en/master/). "OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs". (**[IEEE Micro, 2020](https://ieeexplore.ieee.org/abstract/document/9098028/)**)
- WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial - FPGA-PCIe-XDMA-Tutorial?style=social"/> : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
- pulp-platform/axi - platform/axi?style=social"/> : AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.
- hdl-util/hdmi - util/hdmi?style=social"/> : Send video/audio over HDMI on an FPGA. [purisa.me/blog/hdmi-released/](https://purisa.me/blog/hdmi-released/)
- WangXuan95/FPGA-CAN - CAN?style=social"/> : An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
- WangXuan95/FPGA-SDcard-Reader - SDcard-Reader?style=social"/> : An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
- WangXuan95/FPGA-SDcard-Reader-SPI - SDcard-Reader-SPI?style=social"/> : An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
- WangXuan95/FPGA-SDfake - SDfake?style=social"/> : Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
- WangXuan95/FPGA-NFC - NFC?style=social"/> : Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。
- WangXuan95/FPGA-USB-Device - USB-Device?style=social"/> : An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
- WangXuan95/FPGA-CAN - CAN?style=social"/> : An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
- pulp-platform/axi - platform/axi?style=social"/> : AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.
- hdl-util/hdmi - util/hdmi?style=social"/> : Send video/audio over HDMI on an FPGA. [purisa.me/blog/hdmi-released/](https://purisa.me/blog/hdmi-released/)
- WangXuan95/FPGA-SDcard-Reader - SDcard-Reader?style=social"/> : An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
- WangXuan95/FPGA-SDcard-Reader-SPI - SDcard-Reader-SPI?style=social"/> : An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
- WangXuan95/FPGA-SDfake - SDfake?style=social"/> : Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
- WangXuan95/FPGA-NFC - NFC?style=social"/> : Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。
- WangXuan95/FPGA-SATA-HBA - SATA-HBA?style=social"/> : A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
- WangXuan95/FPGA-DAC-R2R-PWM - DAC-R2R-PWM?style=social"/> : FPGA-based 14bit DAC with resistance network and PWM.
- apertus-open-source-cinema/axiom-firmware - open-source-cinema/axiom-firmware?style=social"/> : AXIOM Beta Software. Firmware required to boot & operate the [apertus° AXIOM Beta Camera](https://www.apertus.org/axiom-beta). "微信公众号「OpenFPGA」《[世界上最伟大的开源作品-基于FPGA的开源摄影机--Axiom Camera](https://mp.weixin.qq.com/s/MVLeBwgpCvKlrqwaNzv4dA)》"。
- ChFrenkel/tinyODIN - Cost Digital Spiking Neural Network (SNN) Processor.
- ChFrenkel/ODIN
- ChFrenkel/ReckOn - Chip Learning over Second-Long Timescales.
- Xilinx/Vitis-AI - AI?style=social"/> : Vitis AI offers a unified set of high-level C++/Python programming APIs to run AI applications across edge-to-cloud platforms, including DPU for Alveo, and DPU for Zynq Ultrascale+ MPSoC and Zynq-7000. It brings the benefits to easily port AI applications from cloud to edge and vice versa. 10 samples in [VART Samples](https://github.com/Xilinx/Vitis-AI/tree/master/demo/VART) are available to help you get familiar with the unfied programming APIs. [Vitis-AI-Library](https://github.com/Xilinx/Vitis-AI/tree/master/demo/Vitis-AI-Library) provides an easy-to-use and unified interface by encapsulating many efficient and high-quality neural networks.
- tensil-ai/tensil - ai/tensil?style=social"/> : Open source machine learning accelerators. [www.tensil.ai](https://www.tensil.ai/)
- 19801201/SpinalHDL_CNN_Accelerator
- ZFTurbo/MobileNet-in-FPGA - in-FPGA?style=social"/> : Generator of verilog description for FPGA MobileNet implementation.
- MasLiang/CNN-On-FPGA - On-FPGA?style=social"/> : This is the code of the CNN on FPGA.But this can only be used for reference at present for some files are write coarsly using ISE.
- PipeCNN - based FPGA Accelerator for Large-Scale Convolutional Neural Networks (CNNs).
- WangXuan95/FPGA-SATA-HBA - SATA-HBA?style=social"/> : A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
- WangXuan95/FPGA-DAC-R2R-PWM - DAC-R2R-PWM?style=social"/> : FPGA-based 14bit DAC with resistance network and PWM.
- apertus-open-source-cinema/axiom-firmware - open-source-cinema/axiom-firmware?style=social"/> : AXIOM Beta Software. Firmware required to boot & operate the [apertus° AXIOM Beta Camera](https://www.apertus.org/axiom-beta). "微信公众号「OpenFPGA」《[世界上最伟大的开源作品-基于FPGA的开源摄影机--Axiom Camera](https://mp.weixin.qq.com/s/MVLeBwgpCvKlrqwaNzv4dA)》"。
- ChFrenkel/tinyODIN - Cost Digital Spiking Neural Network (SNN) Processor.
- ChFrenkel/ODIN
- ChFrenkel/ReckOn - Chip Learning over Second-Long Timescales.
- Xilinx/Vitis-AI - AI?style=social"/> : Vitis AI offers a unified set of high-level C++/Python programming APIs to run AI applications across edge-to-cloud platforms, including DPU for Alveo, and DPU for Zynq Ultrascale+ MPSoC and Zynq-7000. It brings the benefits to easily port AI applications from cloud to edge and vice versa. 10 samples in [VART Samples](https://github.com/Xilinx/Vitis-AI/tree/master/demo/VART) are available to help you get familiar with the unfied programming APIs. [Vitis-AI-Library](https://github.com/Xilinx/Vitis-AI/tree/master/demo/Vitis-AI-Library) provides an easy-to-use and unified interface by encapsulating many efficient and high-quality neural networks.
- tensil-ai/tensil - ai/tensil?style=social"/> : Open source machine learning accelerators. [www.tensil.ai](https://www.tensil.ai/)
- 19801201/SpinalHDL_CNN_Accelerator
- ZFTurbo/MobileNet-in-FPGA - in-FPGA?style=social"/> : Generator of verilog description for FPGA MobileNet implementation.
- MasLiang/CNN-On-FPGA - On-FPGA?style=social"/> : This is the code of the CNN on FPGA.But this can only be used for reference at present for some files are write coarsly using ISE.
- PipeCNN - based FPGA Accelerator for Large-Scale Convolutional Neural Networks (CNNs).
- Yu-Zhewen/Tiny_YOLO_v3_ZYNQ - Zhewen/Tiny_YOLO_v3_ZYNQ?style=social"/> : Implement Tiny YOLO v3 on ZYNQ. "A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny". (**[ARC 2020](https://link.springer.com/chapter/10.1007/978-3-030-44534-8_25)**)
- HSqure/ultralytics-pt-yolov3-vitis-ai-edge - pt-yolov3-vitis-ai-edge?style=social"/> : This demo is only used for inference testing of Vitis AI v1.4 and quantitative compilation of DPU. It is compatible with the training results of [ultralytics/yolov3](https://github.com/ultralytics/yolov3) v9.5.0 (it needs to use the model saving method of Pytorch V1.4).
- mcedrdiego/Kria_yolov3_ppe - Time Personal Protective Equipment Detection. "Deep Learning for Site Safety: Real-Time Detection of Personal Protective Equipment". (**[Automation in Construction 2020](https://www.sciencedirect.com/science/article/abs/pii/S0926580519308325)**)
- xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260 - Detection-based-on-YOLOv3-and-KV260?style=social"/> : This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sensing images, and deploys DPU on the KV260 platform to achieve hardware acceleration.
- Pomiculture/YOLOv4-Vitis-AI - Vitis-AI?style=social"/> : Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.
- mkshuvo2/ZCU104_YOLOv3_Post_Processing
- puffdrum/v4tiny_pt_quant - ai-pytorch.
- chanshann/LITE_YOLOV3_TINY_VITISAI
- LukiBa/zybo_yolo - 7000 FPGA board.
- matsuda-slab/YOLO_ZYNQ_MASTER - slab/YOLO_ZYNQ_MASTER?style=social"/> : Implementation of YOLOv3-tiny on FPGA.
- AramisOposich/tiny_YOLO_Zedboard
- FerberZhang/Yolov2-FPGA-CNN- - FPGA-CNN-?style=social"/> : A demo for accelerating YOLOv2 in xilinx's fpga PYNQ.
- shilicon/kr260_robotic_arm - kit. 这是一个在AMD/Xilinx Kria KR260 FPGA板卡上实现机械臂抓取物体的工程。
- sdoira/U96-SLAM - SLAM?style=social"/> : Visual SLAM on Ultra96-V2.
- mkshuvo2/ZCU104_YOLOv3_Post_Processing
- puffdrum/v4tiny_pt_quant - ai-pytorch.
- chanshann/LITE_YOLOV3_TINY_VITISAI
- LukiBa/zybo_yolo - 7000 FPGA board.
- matsuda-slab/YOLO_ZYNQ_MASTER - slab/YOLO_ZYNQ_MASTER?style=social"/> : Implementation of YOLOv3-tiny on FPGA.
- dhm2013724/yolov2_xilinx_fpga - 7000 Soc(PYNQ-z2, Zedboard and ZCU102). (**[硕士论文 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CMFD&dbname=CMFDTEMP&filename=1019228234.nh&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MjE5NTN5dmdXN3JBVkYyNkY3RzZGdFBQcTVFYlBJUjhlWDFMdXhZUzdEaDFUM3FUcldNMUZyQ1VSTE9lWnVkdUY=), [电子技术应用 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDLAST2019&filename=DZJY201908009&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MDU0NDJDVVJMT2VadWR1Rnl2Z1c3ck1JVGZCZDdHNEg5ak1wNDlGYllSOGVYMUx1eFlTN0RoMVQzcVRyV00xRnI=), [计算机科学与探索 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDTEMP&filename=KXTS201910005&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MjkwNzdXTTFGckNVUkxPZVp1ZHVGeXZnVzdyT0xqWGZmYkc0SDlqTnI0OUZZWVI4ZVgxTHV4WVM3RGgxVDNxVHI=)**)
- Yu-Zhewen/Tiny_YOLO_v3_ZYNQ - Zhewen/Tiny_YOLO_v3_ZYNQ?style=social"/> : Implement Tiny YOLO v3 on ZYNQ. "A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny". (**[ARC 2020](https://link.springer.com/chapter/10.1007/978-3-030-44534-8_25)**)
- HSqure/ultralytics-pt-yolov3-vitis-ai-edge - pt-yolov3-vitis-ai-edge?style=social"/> : This demo is only used for inference testing of Vitis AI v1.4 and quantitative compilation of DPU. It is compatible with the training results of [ultralytics/yolov3](https://github.com/ultralytics/yolov3) v9.5.0 (it needs to use the model saving method of Pytorch V1.4).
- mcedrdiego/Kria_yolov3_ppe - Time Personal Protective Equipment Detection. "Deep Learning for Site Safety: Real-Time Detection of Personal Protective Equipment". (**[Automation in Construction 2020](https://www.sciencedirect.com/science/article/abs/pii/S0926580519308325)**)
- xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260 - Detection-based-on-YOLOv3-and-KV260?style=social"/> : This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sensing images, and deploys DPU on the KV260 platform to achieve hardware acceleration.
- Pomiculture/YOLOv4-Vitis-AI - Vitis-AI?style=social"/> : Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.
- AramisOposich/tiny_YOLO_Zedboard
- FerberZhang/Yolov2-FPGA-CNN- - FPGA-CNN-?style=social"/> : A demo for accelerating YOLOv2 in xilinx's fpga PYNQ.
- Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3 - Velicheti/FPGA-Accelerator-for-TinyYolov3?style=social"/> : An FPGA-Accelerator-for-TinyYolov3.
- xbdxwyh/yolov3_fpga_project
- ZLkanyo009/Yolo-compression-and-deployment-in-FPGA - compression-and-deployment-in-FPGA?style=social"/> : 基于FPGA量化的人脸口罩检测。
- xiying-boy/yolov3-AX7350 - boy/yolov3-AX7350?style=social"/> : 基于HLS_YOLOV3的驱动文件。
- himewel/yolowell - design of convolutional neural networks inference at FPGA devices.
- embedeep/Free-TPU - TPU?style=social"/> : Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
- yarakigit/design_contest_yolo_change_ps_to_pl - metal (FPGA implementation).
- adamgallas/fpga_accelerator_yolov3tiny
- Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3 - Velicheti/FPGA-Accelerator-for-TinyYolov3?style=social"/> : An FPGA-Accelerator-for-TinyYolov3.
- xbdxwyh/yolov3_fpga_project
- ZLkanyo009/Yolo-compression-and-deployment-in-FPGA - compression-and-deployment-in-FPGA?style=social"/> : 基于FPGA量化的人脸口罩检测。
- xiying-boy/yolov3-AX7350 - boy/yolov3-AX7350?style=social"/> : 基于HLS_YOLOV3的驱动文件。
- himewel/yolowell - design of convolutional neural networks inference at FPGA devices.
- embedeep/Free-TPU - TPU?style=social"/> : Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.
- yarakigit/design_contest_yolo_change_ps_to_pl - metal (FPGA implementation).
- adamgallas/fpga_accelerator_yolov3tiny
- ylk678910/tiny-yolov3-fpga - yolov3-fpga?style=social"/> : Use an all-programmable SoC board to implement locating and tracking tasks. The hardware algorithm, a row-stationary-like strategy, can parallel calculate and reduce the storage buffer area on FPGA.
- zhen8838/K210_Yolo_framework
- TonyZ1Min/yolo-for-k210 - for-k210?style=social"/> : keras-yolo-for-k210.
- vseasky/yolo-for-k210 - for-k210?style=social"/> : Yolo-for-k210.
- shilicon/kr260_robotic_arm - kit. 这是一个在AMD/Xilinx Kria KR260 FPGA板卡上实现机械臂抓取物体的工程。
- sdoira/U96-SLAM - SLAM?style=social"/> : Visual SLAM on Ultra96-V2.
- WangXuan95/FPGA-JPEG-LS-encoder - JPEG-LS-encoder?style=social"/> : An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图象压缩。
- WangXuan95/FPGA-MPEG2-encoder - MPEG2-encoder?style=social"/> : FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
- WangXuan95/UH-JLS - JLS?style=social"/> : FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图象压缩。
- WangXuan95/Verilog-FixedPoint - FixedPoint?style=social"/> : A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
- ylk678910/tiny-yolov3-fpga - yolov3-fpga?style=social"/> : Use an all-programmable SoC board to implement locating and tracking tasks. The hardware algorithm, a row-stationary-like strategy, can parallel calculate and reduce the storage buffer area on FPGA.
- zhen8838/K210_Yolo_framework
- vseasky/yolo-for-k210 - for-k210?style=social"/> : Yolo-for-k210.
- WangXuan95/FPGA-JPEG-LS-encoder - JPEG-LS-encoder?style=social"/> : An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图象压缩。
- WangXuan95/FPGA-MPEG2-encoder - MPEG2-encoder?style=social"/> : FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
- WangXuan95/UH-JLS - JLS?style=social"/> : FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图象压缩。
- WangXuan95/Verilog-FixedPoint - FixedPoint?style=social"/> : A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
- XiangShan (香山) - source high-performance RISC-V processor project. "Towards Developing High Performance RISC-V Processors Using Agile Methodology". (**[MICRO 2022](https://ieeexplore.ieee.org/abstract/document/9923860/)**)
- WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial - FPGA-PCIe-XDMA-Tutorial?style=social"/> : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。
- WangXuan95/FPGA-DDR-SDRAM - DDR-SDRAM?style=social"/> : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
- WangXuan95/FPGA-USB-Device - USB-Device?style=social"/> : An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
- WangXuan95/FPGA-FOC - FOC?style=social"/> : FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
- dhm2013724/yolov2_xilinx_fpga - 7000 Soc(PYNQ-z2, Zedboard and ZCU102). (**[硕士论文 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CMFD&dbname=CMFDTEMP&filename=1019228234.nh&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MjE5NTN5dmdXN3JBVkYyNkY3RzZGdFBQcTVFYlBJUjhlWDFMdXhZUzdEaDFUM3FUcldNMUZyQ1VSTE9lWnVkdUY=), [电子技术应用 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDLAST2019&filename=DZJY201908009&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MDU0NDJDVVJMT2VadWR1Rnl2Z1c3ck1JVGZCZDdHNEg5ak1wNDlGYllSOGVYMUx1eFlTN0RoMVQzcVRyV00xRnI=), [计算机科学与探索 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ&dbname=CJFDTEMP&filename=KXTS201910005&uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!&v=MjkwNzdXTTFGckNVUkxPZVp1ZHVGeXZnVzdyT0xqWGZmYkc0SDlqTnI0OUZZWVI4ZVgxTHV4WVM3RGgxVDNxVHI=)**)
Awesome List
- Vitorian/awesome-fpga - fpga?style=social"/> : A collection of resources on FPGA devices and development in general.
- drom/awesome-hdl - hdl?style=social"/> : A curated list of amazingly awesome hardware description language projects.
- ben-marshall/awesome-open-hardware-verification - marshall/awesome-open-hardware-verification?style=social"/> : A curated List of Free and Open Source hardware verification tools and frameworks.
- kelu124/awesome-latticeFPGAs - latticeFPGAs?style=social"/> : 📖 List of FPGA Lattice boards using open tools.
- FPGA-Systems/fpga-awesome-list - Systems/fpga-awesome-list?style=social"/> : fpga-awesome-list. Полезные ресурсы по тематике FPGA / ПЛИС.
- hdl/awesome
- emanueledelsozzo/awesome-fpga-programming - fpga-programming?style=social"/> : A curated list of awesome languages and tools to program FPGAs.
- emanueledelsozzo/awesome-fpga-programming - fpga-programming?style=social"/> : A curated list of awesome languages and tools to program FPGAs.
- Vitorian/awesome-fpga - fpga?style=social"/> : A collection of resources on FPGA devices and development in general.
- kelu124/awesome-latticeFPGAs - latticeFPGAs?style=social"/> : 📖 List of FPGA Lattice boards using open tools.
- FPGA-Systems/fpga-awesome-list - Systems/fpga-awesome-list?style=social"/> : fpga-awesome-list. Полезные ресурсы по тематике FPGA / ПЛИС.
- hdl/awesome
- vhdl/awesome-vhdl - vhdl?style=social"/> : A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
- vhdl/awesome-vhdl - vhdl?style=social"/> : A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.
- clin99/awesome-eda - eda?style=social"/> : A curated list of EDA open source projects.
- clin99/awesome-eda - eda?style=social"/> : A curated list of EDA open source projects.
- iDoka/awesome-fpga-boards - fpga-boards?style=social"/> : List of Repurposed FPGA boards which getting Second life in DYI or Hobby projects.
- iDoka/awesome-fpga-boards - fpga-boards?style=social"/> : List of Repurposed FPGA boards which getting Second life in DYI or Hobby projects.
- TM90/awesome-hwd-tools - hwd-tools?style=social"/> : A curated list of awesome open source hardware design tools.
- TM90/awesome-hwd-tools - hwd-tools?style=social"/> : A curated list of awesome open source hardware design tools.
- qninth/awesome-digital-ic - digital-ic?style=social"/> : A collection of great digital IC project/tutorial/website etc..
- qninth/awesome-digital-ic - digital-ic?style=social"/> : A collection of great digital IC project/tutorial/website etc..
- fukatani/awesome-hdl - hdl?style=social"/> : A curated list of awesome HDL, libraries, typical implementation and references.
- fukatani/awesome-hdl - hdl?style=social"/> : A curated list of awesome HDL, libraries, typical implementation and references.
- mikeroyal/VHDL-Guide - Guide?style=social"/> : A guide covering VHDL including the applications, libraries and tools that will make you a better and more efficient with VHDL development.
- mikeroyal/VHDL-Guide - Guide?style=social"/> : A guide covering VHDL including the applications, libraries and tools that will make you a better and more efficient with VHDL development.
- mikeroyal/Verilog-SystemVerilog-Guide - SystemVerilog-Guide?style=social"/> : Verilog/SystemVerilog Guide. A guide covering Verilog & SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.
- analogdevicesinc/hdl
- analogdevicesinc/hdl
- mikeroyal/Verilog-SystemVerilog-Guide - SystemVerilog-Guide?style=social"/> : Verilog/SystemVerilog Guide. A guide covering Verilog & SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.
- analogdevicesinc/hdl
- analogdevicesinc/hdl

Programming Languages

Verilog 32 C 30 Python 29 Scala 13 SystemVerilog 11 VHDL 10 Rust 9 Jupyter Notebook 6 Shell 4 C++ 3

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Experiments

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awesome-fpga

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Awesome List