https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/carlkidcrypto/digital-systems-engineering

A repo for ECE 440 (Digital Systems Engineering) class projects

systemverilog verilog xilinx-vivado zynq

Last synced: 16 Dec 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 02 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

fpu verilog

Last synced: 02 Dec 2024

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 08 Dec 2024

https://github.com/lovc21/vhdl-code-from-lab

This repository includes VHDL code for laboratory projects conducted in an Integrated Circuits and Design course. It particularly emphasizes the 'Generator Tonov Jakob' project, which has been enhanced to showcase varying frequencies and tones. For detailed insights into these projects, refer to the course website.

verilog vhdl vhdl-code

Last synced: 19 Jan 2025

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 03 Dec 2024

https://github.com/rogerfan48/course-soph1-hdl

Materials and coursework for Hardware Design Lab (Sophomore Fall). Contains exercises, assignments, and laboratory work.

verilog vivado

Last synced: 08 Jan 2025

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/limpix31/tangmega138kpro-blink

fpga hardware-design hdl system-verilog verilog

Last synced: 07 Jan 2025

https://github.com/sea-n/nctu-108b-dcd

108 Spring - Digital Circuit Design

homework nctu verilog

Last synced: 07 Jan 2025

https://github.com/kenny2github/verilog-cpu

A very rudimentary and haphazard CPU created in Verilog.

cpu verilog verilog-hdl

Last synced: 20 Dec 2024

https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

fpga nexus-3 pipelined uart verilog

Last synced: 23 Dec 2024

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 04 Dec 2024

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 04 Dec 2024

https://github.com/vlad-ivanov-name/verilog-zeroall

Resets all register to zero in a Verilog design

modelsim verilog

Last synced: 04 Dec 2024

https://github.com/yappy2000d/fpga-make-win

Use the make tool to automate your work in CLI.

makefile quartus verilog

Last synced: 25 Jan 2025

https://github.com/elifgokpinar/microprocessor-design

Quartus Project

microprocessor quartus verilog

Last synced: 13 Jan 2025

https://github.com/fuwn/iverilog-test-bench

☀️ Icarus Verilog Test-bench Template

de10 icarus-verilog verilog

Last synced: 10 Dec 2024

https://github.com/andrejchoo/cpldctrum

ZX Spectrum clone on CPLD

cpld divmmc verilog zx-spectrum

Last synced: 11 Dec 2024

https://github.com/andrejchoo/avr_like_core_on_verilog

Soft core with support for the AVR8 instructions on verilog

avr soft-core verilog

Last synced: 11 Dec 2024

https://github.com/roscibely/arithmetic-logic-unit

A simple arithmetic logic unit (ALU) with System verilog

alu arithmetic verilog vhdl

Last synced: 21 Jan 2025

https://github.com/pseudoincorrect/verilog_labs

Verilog labs

c dsp soft-cpu verilog

Last synced: 16 Dec 2024

https://github.com/seojuncha/fromthetransistor-fork

geohot's fromthetransistor project. Create a repo on my own because of the contribution map!!

assembler assembly c compiler fromthetransistor python uart verilog

Last synced: 11 Dec 2024

https://github.com/yasnakateb/threshold

🖼✏️ My first baby steps into the world of image processing

grayscale image-processing threshold verilog verilog-hdl xilinx-ise

Last synced: 20 Jan 2025

https://github.com/mohammadmahdi-abdolhosseini/computer-architecture-lab

Computer Architecture Lab - Assignments - Fall 2023

arm-processor fpga modelsim quartus2 systemverilog verilog vhdl

Last synced: 07 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/mosure/ece552-project-fall-2018

ece552 uw-madison verilog

Last synced: 27 Jan 2025

https://github.com/skpro-glitch/resume

Find my resume, encapsulating my most prominent projects and experiences relevant for an entry level Hardware Engineering role. - Soham Kapur

algorithms-and-data-structures cadence cadence-virtuoso drone electronics-engineering java java-programming ltspice matlab soham-kapur sohamkapur team-aviators-international uav verilog verilog-hdl verilog-processor vit-chennai vit-university vitc vitchennai

Last synced: 12 Dec 2024

https://github.com/kaushalmodi/nim-svvpi

Wrapper for SystemVerilog VPI headers sv_vpi_user.h and vpi_user.h

1364-2005 1800-2017 nim pli systemverilog verilog vpi

Last synced: 16 Jan 2025

https://github.com/abstractmachines/verilog-shift-register

A shift register in Verilog. Bidirectional pin use.

embedded-systems hardware shift-register verilog

Last synced: 12 Dec 2024

https://github.com/jminjares4/digital-system-2-template

Digital System 2 Template

digital-design verilog

Last synced: 10 Jan 2025

https://github.com/mtaciano/fpgmips

Um processador baseado na arquitetura MIPS 32bits no FPGA DE2-115.

fpga mips processor verilog

Last synced: 12 Dec 2024

https://github.com/rehankarthikchandralal/implementation-of-a-configurable-neural-processing-unit-with-input-and-weight-stationary-dataflows

Used Verilog to design an entire NPU that supports two different kinds of dataflows to enable data reuse in order to reduce power consumption and resource utilization

neural-network-hardware verilog

Last synced: 17 Dec 2024

https://github.com/kitune-san/kfmmc_v2

Multi media card access controller written in HDL

hdl mmc multimediacard sdc sdcard verilog verilog-hdl

Last synced: 21 Jan 2025

https://github.com/shuregg/riscv-simple-cpu

Creating a risc-v processor

cpu risc-v riscv riscv32 rtl systemverilog verification verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/shuregg/fpga-practicum

learning about FPGA

fpga fpga-programming rtl systemverilog verilog vivado xilinx

Last synced: 13 Dec 2024

https://github.com/shuregg/miet-interfaces

Interfaces of computing systems

interfaces protocols verilog verilog-hdl

Last synced: 13 Dec 2024

https://github.com/kitune-san/kf76489

KF76489 - 76489-like Digital Complex Sound generator written in SystemVerilog

fpga sn76489 systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/markmll/todaystart-a153

As-shipped demo for the Altera Cyclone TodayStart-A153 board. Requires Quartus-II 10.1 SP1 minimum.

fpga verilog vhdl

Last synced: 21 Dec 2024

https://github.com/lasithaamarasinghe/uart-implementation-in-fpga

This is a group assignment done under semester 4 module EN2111:Electronic Circuit Design, .

fpga quartus-prime uart verilog

Last synced: 10 Jan 2025

https://github.com/miku-218525/asic_lab

verilog

Last synced: 25 Dec 2024

https://github.com/mssola/hdl

Playing around with Hardware Description Languages.

hdl systemverilog verilog

Last synced: 27 Jan 2025

https://github.com/memgonzales/hdl-flip-flop

Compilation of Verilog behavioral models and test benches for the four types of flip-flops (SR, JK, D, and T)

behavioral-modeling computer-architecture flip-flop sequential-circuits verilog

Last synced: 20 Jan 2025

https://github.com/rainingcomputers/srp16

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

cpu instruction-set-architecture isa isa-specification microcontrollers open-embedded open-isa risc soft-core verilog

Last synced: 21 Dec 2024

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 06 Dec 2024

https://github.com/3-o-3/cod5

Public Domain (⊄) Computer on FPGA

fpga fpga-soc public-domain ternary ternary-computer verilog

Last synced: 18 Dec 2024