https://github.com/xigh/tinyfpga-counter

simple 1hz tinyfpga counter

fpga tinyfpga-bx verilog

Last synced: 08 Jan 2025

https://github.com/jackson-nestelroad/verilog-mips-processor

Single-cycle 32-bit MIPS processor implemented in SystemVerilog.

cpu mips processor verilog

Last synced: 01 Dec 2024

https://github.com/rejunity/atari-2600-fpga

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

atari-2600 atari2600 fpga retrogaming verilog

Last synced: 24 Jan 2025

https://github.com/j-m-li/3o3

Ternary CPU for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 06 Dec 2024

https://github.com/tdholmes/digitaldesign-pong

Verilog Pong game designed for Digital Design in December of 2013.

pong verilog

Last synced: 02 Dec 2024

https://github.com/mc256/eecs2021

DO NOT COPY. MAKE SURE U UNDERSTAND.

eecs2021 mips verilog yorkuniversity

Last synced: 24 Jan 2025

https://github.com/aliiiw/computer-architecture-lab

Implement Mips cpu with Verilog

forwarding mips pipeline verilog

Last synced: 02 Dec 2024

https://github.com/chaseruskin/setup-orbit

GitHub Action to install Orbit

action continuous-integration hdl systemverilog utilities verilog vhdl

Last synced: 26 Jan 2025

https://github.com/harikrishnan669/verilog

KTU S4 DIGITAL LAB PROGRAMS (VERILOG)

cse ktu-s4-cse verilog

Last synced: 28 Nov 2024

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group03

RV32IM Pipeline Processor

risc-v verilog

Last synced: 11 Jan 2025

https://github.com/j-m-li/logical16x16

Hardware Description Language for EPROM and FLASH memories

eprom public-domain verilog

Last synced: 18 Nov 2024

https://github.com/prinuvinod/digital-lab

These are some Verilog Programs

digital verilog

Last synced: 06 Jan 2025

https://github.com/abdullahmaqbool22/arithmetic-logic-unit-alu

A final semester project for Digital Logic Data.

dld dld-project verilog

Last synced: 29 Dec 2024

https://github.com/dev-ritik/calculator

Xilinx college project

calculator college-project gui java-applet verilog xilinx

Last synced: 03 Dec 2024

https://github.com/akielaries/hwverif

Sandbox for exploring Hardware Verification

verilog

Last synced: 20 Jan 2025

https://github.com/dpieve/university

A resource for students learning programming and personal reference.

assembly cpp haskell haskell-exercises java matlab prolog python shell unifei-university verilog

Last synced: 22 Dec 2024

https://github.com/susiejojo/sobel_filter

Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4

hdl sobel-filter verilog xilinx-ise

Last synced: 17 Dec 2024

https://github.com/dyna-bytes/fpga_winter_internship_2020

[Korea University Elementary Particle Physics Lab] Hardware control research using FPGA

fpga rtl verilog vhdl

Last synced: 02 Dec 2024

https://github.com/dyna-bytes/fisr

Specialized FPU for Fast Inverse Square Root Algorithm

fpu verilog

Last synced: 02 Dec 2024

https://github.com/ain1084/machxo2_serial_to_spdif_transmitter

Serial (LPCM) to S/PDIF transmitter. Using MachXO2 (1200HC QFN32).

audio machxo2 spdif verilog

Last synced: 20 Dec 2024

https://github.com/lemongrb/digitaldesignwithverilog

Simple circuits designed with verilog

asic behavioural dataflow design digitalsystems fpga structural verilog verilog-code verilog-project verilogprojects

Last synced: 10 Jan 2025

https://github.com/calint/tang-nano-20k--riscv--cache-sdram

RISC-V implementation of rv32i for FPGA board Tang Nano 20K utilizing on-board burst SDRAM and flash

fpga risc-v rv32i systemverilog tang-nano-20k verilog

Last synced: 03 Jan 2025

https://github.com/shiro-raven/verilog-mips

A verilog-based MIPS processor with pipelining

assembly mips mips-architecture verilog

Last synced: 05 Dec 2024

https://github.com/toruniina/brainfxck-circuit

run brainfxck on FPGA

brainfuck verilog

Last synced: 08 Dec 2024

https://github.com/mohammadmahdi-abdolhosseini/digital-logic-courses

Digital Systems 1 & 2 + Digital Systems Laboratory 1 + Digital Electronics Circuit +Microprocessor Based and Embedded Design courses projects

hspice systemverilog verilog

Last synced: 07 Jan 2025

https://github.com/calint/zen-one

experimental retro 16 bit cpu written in verilog xilinx vivado intended for fpga cmod s7 from digilent

16-bit cmod-s7 cpu fpga iverilog verilog vintage vivado

Last synced: 10 Jan 2025

https://github.com/andrejchoo/fpga_wav_player

A simple project for playing wav files on FPGA or CPLD

fpga spi-flash verilog wav

Last synced: 03 Jan 2025

https://github.com/ilyachichkov/verilog_labs_2023

Verilog & C Language practice

drivers fpga hardware low-level verilog

Last synced: 04 Jan 2025

https://github.com/eonu/fpga

Hardware implementations for basic digital circuit designs in Verilog with a Xilinx Artix-7 FPGA chip on a Digilent Basys 3 development board.

artix-7 basys3 circuits digital-design fpga hardware hardware-designs hdl simulation testbench verilog vivado

Last synced: 29 Dec 2024

https://github.com/guntas-13/verilog

Compilation of all the Verilog Assignments in the course ES204 - Digital Systems (Spring 2024) - Prof. Joycee Mekie

verilog verilog-hdl

Last synced: 03 Dec 2024

https://github.com/azazhassankhan/verilogutilitysuite

VerilogUtilitySuite 🚀 Welcome to our SystemVerilog playground! 🤖 Dive into the world of hardware description language (HDL) with our repository, where RTL designs meet creativity.

circuit component-architecture systemverilog verilog

Last synced: 21 Jan 2025

https://github.com/kayejd/nexysa7-fpga-programming

Embedded Programming Projects

embedded-systems fpga-programming verilog vivado

Last synced: 17 Jan 2025

https://github.com/kayejd/hvac-system

School Related Project

capstone digital digital-signal-processing engineering-design verilog

Last synced: 17 Jan 2025

https://github.com/ain1084/audio_level_meter

This is an audio level meter implemented using Verilog HDL.

audio machxo2 verilog visualization

Last synced: 20 Dec 2024

https://github.com/akafael/verilog-sandbox

selflearning tutorial-exercises verilog

Last synced: 29 Nov 2024

https://github.com/kulp/tappy

tappy is a tiny Verilog driver for PS/2 keyboards, for use in FPGAs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/qasimwani/karnaugh-map-batch-calculator

Calculates Multiple Karnaugh Maps at once using Selenium and custom built parser. The program then converts the Boolean Expressions into Dataflow Verilog (VHDL)

converts dataflow-verilog karnaugh-map karnaugh-map-solver karnaugh-maps selenium verilog web-scraping

Last synced: 27 Dec 2024

https://github.com/thedhruvrawat/comparch

This repository contains all the laboratory coursework for the course CS F342: Computer Architechture at BITS Pilani, Pilani Campus (Fall '22)

computer-architecture verilog

Last synced: 03 Jan 2025

https://github.com/anthonyhuang19/fpga-embedded-systems

This project focuses on designing digital circuits and microprocessors using FPGA, covering topics like Boolean logic, combinational circuits, state machines, CPU design, and memory structures (ROM/RAM).

fpga stata verilog

Last synced: 19 Jan 2025

https://github.com/cepdnaclk/e18-co502-rv32im-pipeline-implementation-group4

Single-cycle MIPS-like processor with a memory subsystem including a cache.

computer-architecture risc-v verilog

Last synced: 11 Jan 2025

https://github.com/et312/custom_cpu

Custom 16-bit RISC-based CPU with custom control unit, ALU, and memory block designs

fpga verilog

Last synced: 16 Dec 2024

https://github.com/assem-elqersh/mips-processor-designs

Comprehensive repository containing Verilog implementations of MIPS processors. Includes both single-cycle and multi-cycle architectures, each in separate directories, with full simulation testbenches and modular design components for educational and development purposes.

computer-architecture educational hardware-designs mips mips-architecture processor-design simulation verilog

Last synced: 27 Jan 2025

https://github.com/woolseyworkshop/article-getting-started-with-the-tinyfpga-bx

Getting Started With The TinyFPGA BX Article Resources

electronics programming tinyfpga-bx verilog

Last synced: 29 Dec 2024

https://github.com/samiyaalizaidi/pipelined-risc-v-processor

A Pipelined RISC-V Processor with forwarding support and hazard detection.

assembly computer-architecture pipelining processor processor-architecture risc-v verilog vivado

Last synced: 16 Jan 2025

https://github.com/woolseyworkshop/article-creating-a-configurable-multifunction-logic-gate-in-verilog

Creating A Configurable Multifunction Logic Gate In Verilog Article Resources

digital-logic verilog

Last synced: 29 Dec 2024

https://github.com/abshar-shihab/the-fast-matrix-multiplication-on-fpga

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

fpga nexus-3 pipelined uart verilog

Last synced: 23 Dec 2024

https://github.com/wassimhedfi/fpga_adc_pwm_motorcontrol

This repository contains the implementation of a motor speed control system using an FPGA. The speed is adjusted dynamically through a potentiometer, leveraging ADC for analog-to-digital conversion and PWM for precise motor control.

adc de10-lite fpga html motor-speed pwm verilog vhdl

Last synced: 04 Dec 2024

https://github.com/princeranjan03/imageencryption_i-chip

This project focuses on creating a hardware-based encryption and decryption system that implements the Data Encryption Standard (DES) algorithm.

cipher cryptography data-encryption data-encryption-standard encoding encryption-decryption fpga image image-processing opencv rtldesign source-coding verilog verilog-hdl verilog-project vivado xilinx xilinx-vivado

Last synced: 04 Dec 2024