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Projects in Awesome Lists tagged with hdl
A curated list of projects in awesome lists tagged with hdl .
https://github.com/niqzart/pylohd
High-level framework for simplification and systematization of processes in electronic design
converter hdl python thesis-project verilog
Last synced: 06 Dec 2024
https://github.com/birdybro/nand2tetris_mister
Nand2Tetris for MiSTer (as a learning experience for me).
hdl mister misterfpga tetris verilog verilog-hdl
Last synced: 05 Dec 2024
https://github.com/mssola/hdl
Playing around with Hardware Description Languages.
Last synced: 29 Nov 2024
https://github.com/shohamc1/alchitry-ram
ISTD 50.002 Computation Structures 1D Project [SUTD]
Last synced: 16 Nov 2024
https://github.com/agauniyal/nand2tetris
http://nand2tetris.org/
hdl nand2tetris nand2tetris-assignments
Last synced: 29 Nov 2024
https://github.com/adolbyb/vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Last synced: 19 Nov 2024
https://github.com/man2dev/logic-circuits-and-computer-architecture-lab-course
Some of my Logic Circuits and Computer Architecture Lab projects
hdl logic mips university university-assignment university-course university-project xilinx xilinx-ise xilinx-ise-design-suite
Last synced: 13 Nov 2024
https://github.com/richasavant/icarus-verilog-hdl-logical-circuits-2023
This repository focuses on designing and simulating logical circuits using Verilog HDL (Hardware Description Language) with the Icarus Verilog simulator.
adders arithmetic-circuits combinational-circuit decoders demultiplexer encoders flip-flops hdl icarus-verilog logic-gates multiplexer ripple-carry-adder sequential-circuits shift-registers
Last synced: 14 Nov 2024
https://github.com/waasiq/hack-computer
Implementation of 16 Bit Computer
assembler assembly computer-architecture hdl
Last synced: 20 Nov 2024
https://github.com/luc527/nand2tetris-projects
My solutions to the projects in the "Nand2Tetris" course.
assembler c hdl logic-gates nand2tetris
Last synced: 19 Nov 2024
https://github.com/icarogabryel/flooat
Hardware description language, simulator and python module. It is designed to be friendly, simple, light and productive. More easy to use and learn than Verilog and VHDL.
computer-architecture computer-organization digital-circuits eletronics hardware-description-language hardware-designs hdl integrated-circuits processor-architecture python python-module simulation
Last synced: 17 Nov 2024
https://github.com/susiejojo/sobel_filter
Sobel filter for edge detection in images supporting parallel processing using Verilog on Xilinx ISE 13.4
hdl sobel-filter verilog xilinx-ise
Last synced: 17 Dec 2024
https://github.com/themyle/nand_to_tetris
Nand To Tetris - Building a general purpose computer starting from a NAND gate
hdl logic-gates nand2tetris zig
Last synced: 20 Dec 2024
https://github.com/shoaib1522/digital-logic-design
A comprehensive repository for mastering Digital Logic Design, featuring HDL implementations of the Hack computer, assembler projects, lecture slides, lab assignments, and essential resources for understanding hardware and computer architecture.
asm assembler-implementation computerarchitecture digital hackcomputer hdl logic-programming mano morris python
Last synced: 22 Dec 2024
https://github.com/skippypeanutbutter/nand2tetris
Nand 2 Tetris progression
computer-architecture computer-science hdl
Last synced: 07 Dec 2024
https://github.com/chaseruskin/setup-orbit
GitHub Action to install Orbit
action continuous-integration hdl systemverilog utilities verilog vhdl
Last synced: 27 Nov 2024
https://github.com/wolgwang1729/nand2tetris
This repository contains the implementation of a 16-bit Hack computer based on the Nand2tetris course and the book "The Elements of Computing Systems" by Noam Nisan and Shimon Schocken. The project includes both hardware and software components, demonstrating the construction of a modern computer from basic logic gates.
assembly-language cpu cpu-emulator hdl nand2tetris
Last synced: 15 Dec 2024
https://github.com/dvvcz/viva
Experimental cli to create HDL projects using Vivado, outside of their IDE.
cli hardware hdl package-manager rust systemverilog verilog vivado
Last synced: 09 Nov 2024
https://github.com/alifa98/ca-fall2019
Computer Architecture Lab
circuit computer-architecture hdl logic-circuit vhdl
Last synced: 10 Dec 2024