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RISC-V

Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

GitHub: https://github.com/topics/riscv
Wikipedia: https://en.wikipedia.org/wiki/riscv
Aliases: risc-v, riscv-cpu, riscv-core,
Last updated: 2024-07-29 13:56:57 UTC
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https://github.com/Tencent/ncnn

ncnn is a high-performance neural network inference framework optimized for the mobile platform

android arm-neon artificial-intelligence caffe darknet deep-learning high-preformance inference ios keras mlir mxnet ncnn neural-network onnx pytorch riscv simd tensorflow vulkan

Last synced: 30 Jul 2024

https://github.com/tencent/ncnn

ncnn is a high-performance neural network inference framework optimized for the mobile platform

android arm-neon artificial-intelligence caffe darknet deep-learning high-preformance inference ios keras mlir mxnet ncnn neural-network onnx pytorch riscv simd tensorflow vulkan

Last synced: 03 Aug 2024

https://github.com/unicorn-engine/unicorn

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

arm arm64 cpu cpu-emulator emulator framework m68k mips powerpc reverse-engineering riscv s390x security sparc systemz tricore x86 x86-64

Last synced: 31 Jul 2024

https://github.com/aquynh/capstone

Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.

arm arm64 bpf disassembler ethereum framework m0s65xx m680x m68k mips powerpc reverse-engineering riscv security sparc systemz tms320c64x webassembly x86 x86-64

Last synced: 31 Jul 2024

https://github.com/capstone-engine/capstone

arm arm64 bpf disassembler ethereum framework m0s65xx m680x m68k mips powerpc reverse-engineering riscv security sparc systemz tms320c64x webassembly x86 x86-64

Last synced: 30 Jul 2024

https://github.com/OAID/Tengine

Tengine is a lite, high performance, modular inference engine for embedded device

acl arm artificial-intelligence cnn container cuda machine-learning mips npu nvdla onnx pytorch riscv supperedge tensorflow tensorrt x86-64

Last synced: 31 Jul 2024

https://github.com/rcore-os/rCore

Rust version of THU uCore OS. Linux compatible.

aarch64 mips osdev riscv rust x86-64

Last synced: 01 Aug 2024

https://github.com/misprit7/computerraria

A fully compliant RISC-V computer made inside the game Terraria

logic-gates risc-v riscv terraria terraria-mod

Last synced: 01 Aug 2024

https://github.com/chipsalliance/rocket-chip

Rocket Chip Generator

chip-generator chisel riscv rocket-chip rtl scala

Last synced: 31 Jul 2024

https://github.com/SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Last synced: 30 Jul 2024

https://github.com/darklife/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog

Last synced: 30 Jul 2024

https://github.com/riscv-boom/riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

berkeley boom chisel riscv riscv-boom rocket-chip rtl scala

Last synced: 31 Jul 2024

https://github.com/sipeed/MaixPy-v1

MicroPython for K210 RISC-V, let's play with edge AI easier

aiot edge-ai firmware k210 maixpy micropython riscv

Last synced: 31 Jul 2024

https://github.com/oreboot/oreboot

oreboot is a fork of coreboot, with C removed, written in Rust.

bootloader firmware hacktoberfest linux oreboot os riscv rust

Last synced: 31 Jul 2024

https://github.com/probe-rs/probe-rs

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

arm arm-cores coresight daplink debug debug-probes jlink probe-rs riscv rust stlink

Last synced: 01 Aug 2024

https://github.com/ucb-bar/chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar

Last synced: 02 Aug 2024

https://github.com/stnolting/neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl

Last synced: 31 Jul 2024

https://github.com/o8vm/octox

Unix-like OS in Rust inspired by xv6-riscv

osdev riscv rust xv6-riscv

Last synced: 01 Aug 2024

https://github.com/TheThirdOne/rars

RARS -- RISC-V Assembler and Runtime Simulator

assembler education ide mars risc-v riscv simulator

Last synced: 31 Jul 2024

https://github.com/riscv-mcu/e203_hbirdv2

The Ultra-Low Power RISC-V Core

china core cpu e203 fpga hummingbird low-power nuclei risc-v riscv soc verilog

Last synced: 30 Jul 2024

https://github.com/sysprog21/shecc

A self-hosting and educational C optimizing compiler

arm armv7 c compiler compiler-optimization cross-compiler elf linux qemu risc-v riscv rv32i rv32im self-hosting

Last synced: 01 Aug 2024

https://github.com/rustsbi/rustsbi

RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.

bare-metal riscv rust rust-embedded rustsbi sbi sbi-specification

Last synced: 01 Aug 2024

https://github.com/openhwgroup/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

riscv riscv32imfc

Last synced: 31 Jul 2024

https://github.com/LekKit/RVVM

The RISC-V Virtual Machine

c emulation emulator emulators instruction-decoding jit linux risc risc-v riscv riscv-emulator riscv-linux riscv-simulator riscv32 riscv64 rvvm tracing-jit translation virtual-machine vm

Last synced: 04 Aug 2024

https://github.com/syntacore/scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core ip risc-v riscv rtl rv32e rv32emc rv32i rv32imc verilog

Last synced: 31 Jul 2024

https://github.com/chipsalliance/Cores-VeeR-EH1

VeeR EH1 core

ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital

Last synced: 02 Aug 2024

https://github.com/eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx

Last synced: 02 Aug 2024

https://github.com/d0iasm/rvemu

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).

emulator riscv riscv-emulator riscv-simulator rust

Last synced: 01 Aug 2024

https://github.com/michaeljclark/rv8

RISC-V simulator for x86-64

binary-translation disassembler emulator histogram isa linux macro-op-fusion metadata risc riscv rv-jit rv-meta rv-sim rv-sys rv8 simulator

Last synced: 02 Aug 2024

https://github.com/eunomia-bpf/eunomia-bpf

Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images

bcc ebpf ebpf-co-re function-as-a-service libbpf linux oci oci-image oras riscv wasm webassembly

Last synced: 17 Aug 2024

https://github.com/takahirox/riscv-rust

RISC-V processor emulator written in Rust+WASM

cpu emulator processor risc-v riscv rust wasm webassembly

Last synced: 01 Aug 2024

https://github.com/sergeykhbr/riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

cpu debugger qt riscv simulator soc systemc vhdl

Last synced: 02 Aug 2024

https://github.com/libriscv/libriscv

The fastest RISC-V sandbox

binary-translation cmake cpp cpp20 emulator interpreter jit lightweight low-latency multi-platform no-dependencies risc-v riscv riscv-emulator ultra-low-latency userspace zero-dependency

Last synced: 02 Aug 2024

https://github.com/ucb-bar/riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

chisel riscv rtl

Last synced: 31 Jul 2024

https://github.com/mikeroyal/RISC-V-Guide

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization

Last synced: 30 Jul 2024

https://github.com/jameslzhu/riscv-card

An unofficial assembly reference for RISC-V.

asm berkeley isa latex reference riscv

Last synced: 31 Jul 2024

https://github.com/splinedrive/kianRiscV

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .

cpu cyclone10lp divider ecp5 fpga ice40 ice40hx1k icebreaker icefun icoboard linux linuxsoc multiplier pipelined qmtech-board riscv rv32im softcpu ulx3s verilog

Last synced: 02 Aug 2024

https://github.com/ariya/FastLZ

Small & portable byte-aligned LZ77 compression

amd64 ansi-c arm64 c c90 c99 compression dos fastlz freedos intel lempel-ziv lz77 mipsel ms-dos portable riscv

Last synced: 03 Aug 2024

https://github.com/larsbrinkhoff/lbForth

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

6502 8051 arm asmjs avr compiler cortex-m forth interpreter linux m68k metacompiler msp430 pdp11 programming-language risc-v riscv self-hosted x86

Last synced: 02 Aug 2024

https://github.com/andrescv/jupiter

RISC-V Assembler and Runtime Simulator

asm assembler education risc risc-v riscv riscv-simulator runtime runtime-simulator rv32 rv32g simulator

Last synced: 02 Aug 2024

https://github.com/andrescv/Jupiter

RISC-V Assembler and Runtime Simulator

asm assembler education risc risc-v riscv riscv-simulator runtime runtime-simulator rv32 rv32g simulator

Last synced: 31 Jul 2024

https://github.com/f32c/f32c

A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

altera arduino fpga lattice mips riscv xilinx

Last synced: 02 Aug 2024

https://github.com/arcemu/arcemu

World Of Warcraft 3.3.5a server

aarch64 amd64 arm64 c-plus-plus cmake cpp docker docker-compose lua mysql python risc-v riscv riscv64 vagrant warcraft world-of-warcraft worldofwarcraft wotlk wow

Last synced: 31 Jul 2024

https://github.com/d0iasm/rvemu-for-book

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

emulator riscv riscv-emulator rust xv6

Last synced: 09 Aug 2024

https://github.com/nervosnetwork/ckb-vm

CKB's vm, based on open source RISC-V ISA

blockchain ckb nervos riscv rust smart-contract

Last synced: 01 Aug 2024

https://github.com/pulp-platform/ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

ara asic cpu riscv rv64gcv rvv vector

Last synced: 01 Aug 2024

https://github.com/WangXuan95/USTC-RVSoC

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog

Last synced: 02 Aug 2024

https://github.com/windelbouwman/ppci

A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python

arm assembler c-compiler c-preprocessor compiler m68k msp430 python riscv webassembly x86-64 xtensa

Last synced: 03 Aug 2024

https://github.com/sld-columbia/esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

accelerators asic embedded-systems fpga network-on-chip riscv system-on-chip

Last synced: 01 Aug 2024

https://github.com/Wren6991/Hazard3

3-stage RV32IMACZb* processor with debug

jtag risc-v riscv

Last synced: 16 Aug 2024

https://github.com/riscv-software-src/homebrew-riscv

homebrew (macOS) packages for RISC-V toolchain

homebrew macos riscv

Last synced: 02 Aug 2024

https://github.com/HUST-OS/tornado-os

异步内核就像风一样快！

asynchronous-kernel riscv rust

Last synced: 02 Aug 2024

https://github.com/mrLSD/riscv-fs

F# RISC-V Instruction Set formal specification

cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64

Last synced: 02 Aug 2024

https://github.com/sifive/freedom-u-sdk

Freedom U Software Development Kit (FUSDK)

openembedded riscv sifive yocto

Last synced: 04 Aug 2024

https://github.com/chipsalliance/Cores-VeeR-EL2

VeeR EL2 Core

ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital

Last synced: 01 Aug 2024

https://github.com/QQxiaoming/quard_star_tutorial

This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development board. 本项目旨在真正从0开始构建嵌入式linux系统，为了剖析芯片从上电开始执行第一条指令到整个系统运行，基于qemu定制模拟器开发板。

embedded-linux qemu qemu-riscv riscv riscv-emulator riscv-linux riscv-simulator tutorials

Last synced: 31 Jul 2024

https://github.com/bu-icsg/dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

chisel hardware neural-network riscv rocc rocket-chip rtl

Last synced: 03 Aug 2024

https://github.com/pulp-platform/riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

debug riscv

Last synced: 01 Aug 2024

https://github.com/skyzh/RISCV-Simulator

💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.

branch-prediction cmake computer-architecture cpp cpu gtest pipeline riscv riscv-emulator riscv-simulator riscv32 speculation tomasulo-algorithm

Last synced: 31 Jul 2024

https://github.com/tilk/riscv-simple-sv

A simple RISC V core for teaching

risc-v riscv verilog

Last synced: 02 Aug 2024

https://github.com/CTSRD-CHERI/cheribsd

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

cheri cheribsd freebsd morello riscv

Last synced: 03 Aug 2024

https://github.com/SpinalHDL/SaxonSoc

SoC based on VexRiscv and ICE40 UP5K

riscv rtl soc

Last synced: 02 Aug 2024

https://github.com/pulp-platform/cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

asic fpga riscv rtl-design simulation systemverilog

Last synced: 02 Aug 2024

https://github.com/dineshannayya/riscduino

Arduino compatible Risc-V Based SOC

analog ar i2c pwm qspi riscv usb-host

Last synced: 02 Aug 2024

https://github.com/riscv-steel/riscv-steel

Free and open collection of RISC-V IP.

core cores embedded-systems ip processors risc-v riscv rv32i systems-on-chip-design uart zicsr

Last synced: 02 Aug 2024

https://github.com/thu-cs-lab/supervisor-rv

计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位

riscv

Last synced: 02 Aug 2024

https://github.com/siriusdemon/Rare

Build your own Riscv Emulator in Rust.

emulator riscv rust

Last synced: 02 Aug 2024

https://github.com/microdynamics-cpu/tree-core-ide

:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

chisel3 ide processor riscv simualtion verilog vscode-extension waveform webgl

Last synced: 30 Jul 2024

https://github.com/pulp-platform/hero

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

computer-architecture fpga heterogeneous-computing heterogeneous-parallel-programming iommu many-core-architectures openmp-offloading openmp-parallelization riscv shared-memory unified-virtual-memory

Last synced: 01 Aug 2024

https://github.com/fnuecke/sedna

Sedna - a pure Java RISC-V emulator.

emulator java risc-v riscv

Last synced: 04 Aug 2024

https://github.com/howardlau1999/yatcpu

Yet another toy CPU.

chisel-generator chisel3 cpu risc-v riscv

Last synced: 09 Aug 2024

https://github.com/pulp-platform/pulp_soc

pulp_soc is the core building component of PULP based SoCs

pulp riscv systemverilog

Last synced: 02 Aug 2024

https://github.com/riscv-rust/k210-hal

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

embedded-hal k210 kendryte riscv rust rust-embedded

Last synced: 01 Aug 2024

https://github.com/storage-db/nerdos

一种支持多种架构嵌入式领域的实时操作系统，支持网络通信和grub启动

aarch64 riscv rtos x86-64

Last synced: 02 Aug 2024

https://github.com/mohanson/wasc

WebAssembly AOT compiler

compiler riscv webassembly

Last synced: 07 Aug 2024

https://github.com/jjyr/jonesforth_riscv

Jonesforth RISC-V port.

forth jonesforth riscv

Last synced: 04 Aug 2024

https://github.com/IBM/rocc-software

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

riscv rocc rocket-chip

Last synced: 02 Aug 2024

https://github.com/lcq2/risc-666

RISC-V user-mode emulator that runs DooM

doom emulation graphics risc-v riscv sdl sdl2

Last synced: 31 Jul 2024

https://github.com/OpenMachine-ai/tinyfive

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

ai assembler assembly compiler machine-learning ml risc-v risc-v-32-simulation risc-v-simulator riscv riscv-asm riscv-assembler riscv-assembly riscv-emulator riscv-simulator riscv32

Last synced: 03 Aug 2024

https://github.com/chipsalliance/riscv-vector-tests

Unit tests generator for RVV 1.0

generator riscv rvv spike testsuite

Last synced: 02 Aug 2024

https://github.com/KuangjuX/hypocaust

hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.

hypervisor riscv rust vmm

Last synced: 02 Aug 2024

https://github.com/michaeljclark/riscv-meta

RISC-V Instruction Set Metadata

metadata risc risc-v riscv

Last synced: 01 Aug 2024

https://github.com/microdynamics-cpu/tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

chisel cpu processor riscv rt-thread rtl scala softcore verilator