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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
- GitHub: https://github.com/topics/riscv
- Wikipedia: https://en.wikipedia.org/wiki/riscv
- Aliases: risc-v, riscv-cpu, riscv-core,
- Last updated: 2024-11-04 00:26:05 UTC
- JSON Representation
https://github.com/Tencent/ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
android arm-neon artificial-intelligence caffe darknet deep-learning high-preformance inference ios keras mlir mxnet ncnn neural-network onnx pytorch riscv simd tensorflow vulkan
Last synced: 25 Oct 2024
https://github.com/tencent/ncnn
ncnn is a high-performance neural network inference framework optimized for the mobile platform
android arm-neon artificial-intelligence caffe darknet deep-learning high-preformance inference ios keras mlir mxnet ncnn neural-network onnx pytorch riscv simd tensorflow vulkan
Last synced: 28 Oct 2024
https://github.com/aquynh/capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
arm arm64 bpf disassembler ethereum framework m0s65xx m680x m68k mips powerpc reverse-engineering riscv security sparc systemz tms320c64x webassembly x86 x86-64
Last synced: 11 Nov 2024
https://github.com/unicorn-engine/unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)
arm arm64 cpu cpu-emulator emulator framework m68k mips powerpc reverse-engineering riscv s390x security sparc systemz tricore x86 x86-64
Last synced: 28 Oct 2024
https://github.com/capstone-engine/capstone
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), BPF, Ethereum VM, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
arm arm64 bpf disassembler ethereum framework m0s65xx m680x m68k mips powerpc reverse-engineering riscv security sparc systemz tms320c64x webassembly x86 x86-64
Last synced: 13 Oct 2024
https://github.com/OAID/Tengine
Tengine is a lite, high performance, modular inference engine for embedded device
acl arm artificial-intelligence cnn container cuda machine-learning mips npu nvdla onnx pytorch riscv supperedge tensorflow tensorrt x86-64
Last synced: 27 Oct 2024
https://github.com/oaid/tengine
Tengine is a lite, high performance, modular inference engine for embedded device
acl arm artificial-intelligence cnn container cuda machine-learning mips npu nvdla onnx pytorch riscv supperedge tensorflow tensorrt x86-64
Last synced: 15 Oct 2024
https://github.com/misprit7/computerraria
A fully compliant RISC-V computer made inside the game Terraria
logic-gates risc-v riscv terraria terraria-mod
Last synced: 15 Oct 2024
https://github.com/chipsalliance/rocket-chip
Rocket Chip Generator
chip-generator chisel riscv rocket-chip rtl scala
Last synced: 12 Oct 2024
https://github.com/riscv-boom/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
berkeley boom chisel riscv riscv-boom rocket-chip rtl scala
Last synced: 15 Oct 2024
https://github.com/sipeed/maixpy-v1
MicroPython for K210 RISC-V, let's play with edge AI easier
aiot edge-ai firmware k210 maixpy micropython riscv
Last synced: 10 Oct 2024
https://github.com/sipeed/MaixPy-v1
MicroPython for K210 RISC-V, let's play with edge AI easier
aiot edge-ai firmware k210 maixpy micropython riscv
Last synced: 28 Oct 2024
https://github.com/oreboot/oreboot
oreboot is a fork of coreboot, with C removed, written in Rust.
bootloader firmware hacktoberfest linux oreboot os riscv rust
Last synced: 09 Oct 2024
https://github.com/ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar
Last synced: 09 Oct 2024
https://github.com/stnolting/neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asic asip cpu embedded fpga gdb microcontroller neorv32 openocd processor risc-v riscv rtl rv32 safety soc soft-core system-on-chip verilog vhdl
Last synced: 27 Oct 2024
https://github.com/sysprog21/shecc
A self-hosting and educational C optimizing compiler
arm armv7 c compiler compiler-optimization cross-compiler elf linux qemu risc-v riscv rv32i rv32im self-hosting ssa-form
Last synced: 09 Oct 2024
https://github.com/rustsbi/rustsbi
RISC-V Supervisor Binary Interface (RISC-V SBI) library in Rust; runs on M or HS mode; good support for embedded Rust ecosystem. For binary download see https://github.com/rustsbi/prototyper.
bare-metal riscv rust rust-embedded rustsbi sbi sbi-specification
Last synced: 05 Nov 2024
https://github.com/openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Last synced: 06 Nov 2024
https://github.com/eugene-tarassov/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx
Last synced: 10 Nov 2024
https://github.com/chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Last synced: 09 Nov 2024
https://github.com/chipsalliance/cores-veer-eh1
VeeR EH1 core
ahb-lite asic-design axi4 fpga fusesoc open-source-hardware processor risc risc-v riscv riscv32 rtl veer verilator western-digital
Last synced: 05 Nov 2024
https://github.com/LekKit/RVVM
The RISC-V Virtual Machine
c emulation emulator emulators instruction-decoding jit linux risc risc-v riscv riscv-emulator riscv-linux riscv-simulator riscv32 riscv64 rvvm tracing-jit translation virtual-machine vm
Last synced: 04 Aug 2024
https://github.com/d0iasm/rvemu
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
emulator riscv riscv-emulator riscv-simulator rust
Last synced: 07 Nov 2024
https://github.com/michaeljclark/rv8
RISC-V simulator for x86-64
binary-translation disassembler emulator histogram isa linux macro-op-fusion metadata risc riscv rv-jit rv-meta rv-sim rv-sys rv8 simulator
Last synced: 05 Nov 2024
https://github.com/eunomia-bpf/eunomia-bpf
Build, Distribute and Run CO-RE eBPF programs easier with JSON and Webassembly OCI images
bcc ebpf ebpf-co-re function-as-a-service libbpf linux oci oci-image oras riscv wasm webassembly
Last synced: 12 Oct 2024
https://github.com/takahirox/riscv-rust
RISC-V processor emulator written in Rust+WASM
cpu emulator processor risc-v riscv rust wasm webassembly
Last synced: 14 Nov 2024
https://github.com/wren6991/hazard3
3-stage RV32IMACZb* processor with debug
Last synced: 12 Nov 2024
https://github.com/libriscv/libriscv
The fastest RISC-V sandbox
binary-translation cmake cpp cpp20 emulator interpreter jit lightweight low-latency multi-platform no-dependencies risc-v riscv riscv-emulator ultra-low-latency userspace zero-dependency
Last synced: 12 Oct 2024
https://github.com/ucb-bar/riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
Last synced: 27 Oct 2024
https://github.com/mikeroyal/RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization
Last synced: 25 Oct 2024
https://github.com/mikeroyal/risc-v-guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization
Last synced: 14 Oct 2024
https://github.com/larsbrinkhoff/lbForth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
6502 8051 arm asmjs avr compiler cortex-m forth interpreter linux m68k metacompiler msp430 pdp11 programming-language risc-v riscv self-hosted x86
Last synced: 09 Nov 2024
https://github.com/larsbrinkhoff/lbforth
Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
6502 8051 arm asmjs avr compiler cortex-m forth interpreter linux m68k metacompiler msp430 pdp11 programming-language risc-v riscv self-hosted x86
Last synced: 26 Oct 2024
https://github.com/splinedrive/kianRiscV
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
cpu cyclone10lp divider ecp5 fpga ice40 ice40hx1k icebreaker icefun icoboard linux linuxsoc multiplier pipelined qmtech-board riscv rv32im softcpu ulx3s verilog
Last synced: 09 Nov 2024
https://github.com/andrescv/jupiter
RISC-V Assembler and Runtime Simulator
asm assembler education risc risc-v riscv riscv-simulator runtime runtime-simulator rv32 rv32g simulator
Last synced: 12 Oct 2024
https://github.com/andrescv/Jupiter
RISC-V Assembler and Runtime Simulator
asm assembler education risc risc-v riscv riscv-simulator runtime runtime-simulator rv32 rv32g simulator
Last synced: 29 Oct 2024
https://github.com/sysprog21/rv32emu
Compact and Efficient RISC-V RV32I[MAFC] emulator
bare-metal elf-parser emulator gdbstub instruction-set-simulator jit-compiler remote-debugging risc-v riscv riscv-emulator riscv-simulator riscv32 rv32imac rv32imf virtual-machine
Last synced: 09 Nov 2024
https://github.com/arcemu/arcemu
World Of Warcraft 3.3.5a server
aarch64 amd64 arm64 c-plus-plus cmake cpp docker docker-compose lua mysql python risc-v riscv riscv64 vagrant warcraft world-of-warcraft worldofwarcraft wotlk wow
Last synced: 13 Oct 2024
https://github.com/d0iasm/rvemu-for-book
Reference implementation for the book "Writing a RISC-V Emulator in Rust".
emulator riscv riscv-emulator rust xv6
Last synced: 09 Aug 2024
https://github.com/windelbouwman/ppci
A compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
arm assembler c-compiler c-preprocessor compiler m68k msp430 python riscv webassembly x86-64 xtensa
Last synced: 12 Oct 2024
https://github.com/nervosnetwork/ckb-vm
CKB's vm, based on open source RISC-V ISA
blockchain ckb nervos riscv rust smart-contract
Last synced: 14 Nov 2024
https://github.com/sld-columbia/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
accelerators asic embedded-systems fpga network-on-chip riscv system-on-chip
Last synced: 03 Nov 2024
https://github.com/riscv-software-src/homebrew-riscv
homebrew (macOS) packages for RISC-V toolchain
Last synced: 09 Nov 2024
https://github.com/Wren6991/Hazard3
3-stage RV32IMACZb* processor with debug
Last synced: 16 Aug 2024
https://github.com/HUST-OS/tornado-os
异步内核就像风一样快！
asynchronous-kernel riscv rust
Last synced: 11 Nov 2024
https://github.com/mrLSD/riscv-fs
F# RISC-V Instruction Set formal specification
cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64
Last synced: 09 Nov 2024
https://github.com/mrlsd/riscv-fs
F# RISC-V Instruction Set formal specification
cpu fs fsharp isa library risc-processor risc-v riscv riscv-emulator riscv-simulator riscv32 riscv64
Last synced: 12 Nov 2024
https://github.com/sifive/freedom-u-sdk
Freedom U Software Development Kit (FUSDK)
openembedded riscv sifive yocto
Last synced: 10 Nov 2024
https://github.com/sysprog21/semu
A minimalist RISC-V system emulator capable of running Linux kernel
emulator linux-kernel risc-v riscv riscv-emulator rv32ima
Last synced: 12 Nov 2024
https://github.com/chipsalliance/Cores-VeeR-EL2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Last synced: 03 Nov 2024
https://github.com/chipsalliance/cores-veer-el2
VeeR EL2 Core
ahb-lite asic-design axi4 el2 fpga fusesoc open-source-hardware processor risc-v riscv riscv32 rtl verilator western-digital
Last synced: 05 Nov 2024
https://github.com/libriscv/rvscript
Fast RISC-V-based scripting backend for game engines
cpp cpp20 game-development gamedev low-latency riscv sandbox scripting-engine
Last synced: 12 Nov 2024
https://github.com/QQxiaoming/quard_star_tutorial
This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development board. 本项目旨在真正从0开始构建嵌入式linux系统，为了剖析芯片从上电开始执行第一条指令到整个系统运行，基于qemu定制模拟器开发板。
embedded-linux qemu qemu-riscv riscv riscv-emulator riscv-linux riscv-simulator tutorials
Last synced: 28 Oct 2024
https://github.com/pulp-platform/riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
Last synced: 07 Nov 2024
https://github.com/bu-icsg/dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
chisel hardware neural-network riscv rocc rocket-chip rtl
Last synced: 03 Aug 2024
https://github.com/pulp-platform/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
asic fpga riscv rtl-design simulation systemverilog
Last synced: 09 Nov 2024
https://github.com/skyzh/RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
branch-prediction cmake computer-architecture cpp cpu gtest pipeline riscv riscv-emulator riscv-simulator riscv32 speculation tomasulo-algorithm
Last synced: 29 Oct 2024
https://github.com/skyzh/riscv-simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
branch-prediction cmake computer-architecture cpp cpu gtest pipeline riscv riscv-emulator riscv-simulator riscv32 speculation tomasulo-algorithm
Last synced: 27 Oct 2024
https://github.com/patryk27/kartoffels
a game where you're given a potato and your job is to implement a firmware for it
fighting-game game mmo real-time risc-v riscv robot rust simulation
Last synced: 01 Nov 2024
https://github.com/openhwgroup/core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
microcontroller openhwgroup riscv systemverilog
Last synced: 06 Nov 2024
https://github.com/limine-bootloader/limine-c-template
A simple template for building a Limine-compliant kernel in C.
aarch64 amd64 arm64 bare-bones barebones c c-language kernel limine limine-bootloader loongarch loongarch64 loongson risc-v riscv riscv64 template x86-64
Last synced: 13 Nov 2024
https://github.com/nuclei-software/nuclei-sdk
Nuclei RISC-V Software Development Kit
embedded-hal embedded-systems fpga-evaluation-board freertos iot-platform makefile nmsis nuclei nuclei-sdk opensource platformio risc-v riscv rt-thread rtos sdk ucosii
Last synced: 13 Nov 2024
https://github.com/drom/awesome-riscv
😎 A curated list of awesome RISC-V implementations
awesome awesome-list hacktoberfest risc-v riscv riscv32 riscv64
Last synced: 03 Oct 2024
https://github.com/thu-cs-lab/supervisor-rv
计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
Last synced: 09 Nov 2024
https://github.com/riscv-steel/riscv-steel
Free and open collection of RISC-V IP.
core cores embedded-systems ip processors risc-v riscv rv32i systems-on-chip-design uart zicsr
Last synced: 10 Nov 2024
https://github.com/esp-rs/esp-pacs
Peripheral Access Crates for Espressif SoCs and modules
Last synced: 10 Oct 2024
https://github.com/microdynamics-cpu/tree-core-ide
:deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
chisel3 ide processor riscv simualtion verilog vscode-extension waveform webgl
Last synced: 25 Oct 2024
https://github.com/pulp-platform/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
computer-architecture fpga heterogeneous-computing heterogeneous-parallel-programming iommu many-core-architectures openmp-offloading openmp-parallelization riscv shared-memory unified-virtual-memory
Last synced: 03 Nov 2024
https://github.com/ittuann/enterprise_e
第十六届智能车竞赛-国家级一等奖-嵌入式控制开源(恩智浦杯/飞思卡尔杯)-全国第14名 🏆
board embedded embedded-c freescale-cup hardware intelligent-car nxp-cup pid riscv smart-car wch
Last synced: 09 Nov 2024
https://github.com/howardlau1999/yatcpu
Yet another toy CPU.
chisel-generator chisel3 cpu risc-v riscv
Last synced: 09 Aug 2024
https://github.com/pulp-platform/pulp_soc
pulp_soc is the core building component of PULP based SoCs
Last synced: 09 Nov 2024
https://github.com/sifive/riscvspecformal
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
coq formal-verification hardware hardware-designs riscv riscv-simulator
Last synced: 12 Oct 2024
https://github.com/seldridge/rocket-rocc-examples
Tests for example Rocket Custom Coprocessors
Last synced: 08 Nov 2024
