https://github.com/seldridge/rocket-rocc-examples

Tests for example Rocket Custom Coprocessors

riscv rocc rocket-chip

Last synced: 08 Nov 2024

https://github.com/mmicko/fpga101-workshop

FPGA 101 - Workshop materials

apio fpga hackaday icestorm icestudio micropython riscv verilog

Last synced: 08 Nov 2024

https://github.com/riscv-rust/k210-hal

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

embedded-hal k210 kendryte riscv rust rust-embedded

Last synced: 05 Nov 2024

https://github.com/storage-db/nerdos

一种支持多种架构嵌入式领域的实时操作系统，支持网络通信和grub启动

aarch64 riscv rtos x86-64

Last synced: 11 Nov 2024

https://github.com/racerxdl/riscv-emulator

Golang RISC-V emulator that can play DOOM

doom emulator golang risc-v riscv toy-emulator

Last synced: 07 Nov 2024

https://github.com/mohanson/wasc

WebAssembly AOT compiler

compiler riscv webassembly

Last synced: 07 Nov 2024

https://github.com/chipsalliance/riscv-vector-tests

Unit tests generator for RVV 1.0

generator riscv rvv spike testsuite

Last synced: 05 Nov 2024

https://github.com/spacemeowx2/blflash

bl602 serial flasher

bl602 flash riscv toolchain

Last synced: 11 Nov 2024

https://github.com/jjyr/jonesforth_riscv

Jonesforth RISC-V port.

forth jonesforth riscv

Last synced: 07 Nov 2024

https://github.com/misyltoad/riscv-vscript

A port of mini-rv32ima to VScript (Squirrel 3)

risc-v riscv rv32ima small source-engine squirrel squirrel-lang team-fortress-2 tf2 valve-games vscript

Last synced: 13 Nov 2024

https://github.com/openmachine-ai/tinyfive

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

ai assembler assembly compiler machine-learning ml risc-v risc-v-32-simulation risc-v-simulator riscv riscv-asm riscv-assembler riscv-assembly riscv-emulator riscv-simulator riscv32

Last synced: 02 Nov 2024

https://github.com/IBM/rocc-software

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

riscv rocc rocket-chip

Last synced: 09 Nov 2024

https://github.com/kuangjux/hypocaust-2

hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine

hypervisor riscv rust vmm

Last synced: 28 Oct 2024

https://github.com/lcq2/risc-666

RISC-V user-mode emulator that runs DooM

doom emulation graphics risc-v riscv sdl sdl2

Last synced: 28 Oct 2024

https://github.com/OpenMachine-ai/tinyfive

TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples

ai assembler assembly compiler machine-learning ml risc-v risc-v-32-simulation risc-v-simulator riscv riscv-asm riscv-assembler riscv-assembly riscv-emulator riscv-simulator riscv32

Last synced: 03 Aug 2024

https://github.com/kuangjux/hypocaust

hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.

hypervisor riscv rust vmm

Last synced: 28 Oct 2024

https://github.com/KuangjuX/hypocaust

hypocaust, a S-mode trap and emulate type-1 hypervisor run on RISC-V machine.

hypervisor riscv rust vmm

Last synced: 11 Nov 2024

https://github.com/64kramsystem/qemu-pinning

My QEMU fork with pinning (affinity) support and a few tweaks.

hypervisor qemu risc-v riscv virtualization

Last synced: 09 Nov 2024

https://github.com/risc0/risc0-lean4

A model of the RISC Zero zkVM and ecosystem in the Lean 4 Theorem Prover

lean lean4 risc-v risc0 riscv riscv32 riscv32im zero-knowledge zk-stark zkvm

Last synced: 11 Nov 2024

https://github.com/dtcxzyw/cmmc

An unofficial reference implementation of the C Minus Minus Compiler

armv7 compiler compiler-design compiler-principles mips32 optimization-compiler riscv

Last synced: 28 Oct 2024

https://github.com/racerxdl/riscv-online-asm

RISC-V Online Assembler using Emscripten, Gnu Binutils

assembler assembly binutils gas risc-v risc-v-assembly riscv

Last synced: 07 Nov 2024

https://github.com/lioncash/biscuit

A runtime code generator for RISC-V

assembly code-generation cpp risc-v riscv

Last synced: 28 Oct 2024

https://github.com/lupyuen/nuttx-ox64

Apache NuttX RTOS for Pine64 Ox64 64-bit RISC-V SBC (BouffaloLab BL808)

bl808 nuttx ox64 riscv riscv64

Last synced: 14 Nov 2024

https://github.com/chuangzhu/nixos-sun20iw1p1

NixOS on Allwinner D1 RISC-V

licheerv linux mangopi riscv sunxi

Last synced: 13 Nov 2024

https://github.com/michaeljclark/riscv-meta

RISC-V Instruction Set Metadata

metadata risc risc-v riscv

Last synced: 05 Nov 2024

https://github.com/rustsbi/rustsbi-tutorial

rustsbi 开发教程

bare-metal riscv sbi

Last synced: 05 Nov 2024

https://github.com/microdynamics-cpu/tree-core-cpu

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

chisel cpu processor riscv rt-thread rtl scala softcore verilator

Last synced: 08 Aug 2024

https://github.com/rustsbi/rustsbi-k210

Kendryte K210 SBI support using RustSBI, provides privileged spec 1.12 environment by emulating it using 1.9.1

riscv rust rust-embedded rustsbi sbi

Last synced: 09 Nov 2024

https://github.com/MaxXSoft/GeeOS

The Gee (寂) Operating System, written in YuLang.

operating-system osdev riscv yulang

Last synced: 11 Nov 2024

https://github.com/nmeum/zig-riscv-embedded

Experimental Zig-based CoAP node for the HiFive1 RISC-V board

bare-metal coap coap-server embedded hifive1 risc-v riscv zig

Last synced: 06 Nov 2024

https://github.com/schorrm/arm2riscv

Arm AArch64 to RISC-V Transpiler

aarch64 arm64 armv8 asm risc risc-v risc-v-assembly risc-v64 riscv riscv-asm riscv-assembly riscv64 rv64gc transpiler

Last synced: 08 Nov 2024

https://github.com/xen0n/larva

PoC LoongArch - RISC-V emulator

loongarch riscv

Last synced: 09 Nov 2024

https://github.com/lupyuen/tcc-riscv32-wasm

TCC (Tiny C Compiler) for 64-bit RISC-V, compiled to WebAssembly with Zig Compiler

nuttx riscv riscv64 romfs tcc webassembly zig ziglang

Last synced: 30 Sep 2024

https://github.com/ibm/ace-riscv

Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for RISC-V with focus on a formally verified and auditable security monitor.

confidential-computing coq formal-verification refinedrust riscv rust-lang security trusted-computing trusted-execution-environment virtualization

Last synced: 12 Nov 2024

https://github.com/jserv/rv32jit

JIT-accelerated RISC-V instruction set simulator

dynamic-binary-translation jit-compiler risc-v riscv riscv-emulator riscv-simulator riscv32

Last synced: 10 Nov 2024

https://github.com/lupyuen/nuttx-sg2000

Apache NuttX RTOS on 64-bit RISC-V Sophgo SG2000 (T-Head C906 / Milk-V Duo S)

duos milkv nuttx riscv riscv64 sg2000 sophgo

Last synced: 14 Nov 2024

https://github.com/platformio/platform-shakti

Shakti: development platform for PlatformIO

platformio platformio-platform risc risc-v riscv

Last synced: 07 Oct 2024

https://github.com/stnolting/neorv32-riscof

✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

ghdl isa neorv32 processor risc-v riscof riscv sail-riscv verification vhdl

Last synced: 09 Nov 2024

https://github.com/lupyuen/nuttx-star64

Apache NuttX RTOS for Pine64 Star64 64-bit RISC-V SBC (StarFive JH7110)

jh7110 nuttx riscv riscv64 star64

Last synced: 14 Nov 2024

https://github.com/sifive/ProcKami

Kami based processor implementations and specifications

coq formal-verification hardware hardware-designs riscv riscv-simulator

Last synced: 09 Nov 2024

https://github.com/rinhizakura/riscv-emulator

A project for learning RISC-V architecture purpose

c emulator riscv riscv-emulator

Last synced: 07 Nov 2024

https://github.com/mr-bossman/kisc-v

KISCV, a KISS principle riscv32i CPU

cpu hdl risc-v riscv riscv32 verilog

Last synced: 30 Oct 2024

https://github.com/sifive/prockami

Kami based processor implementations and specifications

coq formal-verification hardware hardware-designs riscv riscv-simulator

Last synced: 10 Nov 2024

https://github.com/rhysd/toy-riscv-backend

Toy RISC-V LLVM backend

llvm llvm-backend riscv

Last synced: 08 Nov 2024

https://github.com/jiegec/rvv-kernels

Implements kernels with RISC-V Vector

riscv rvv vector

Last synced: 09 Nov 2024

https://github.com/athenavm/athena

Athena monorepo

blockchain riscv spacemesh vm

Last synced: 03 Nov 2024

https://github.com/h1romas4/m5stamp-c3dev

This is a development board for the M5Stamp C3 (RISC-V/FreeRTOS).

arduino arduino-esp32 assemblyscript esp32 esp32c3 jtag m5stack m5stamp risc-v riscv wasm3 webassembly

Last synced: 10 Oct 2024

https://github.com/rcore-os/riscv-sbi-rt

A mininal runtime / startup for Supervisor Binary Interface (SBI) on RISC-V.

riscv rust rustsbi

Last synced: 14 Nov 2024

https://github.com/adamniederer/riscv-mode

Major mode for RISC V assembly

assembly emacs riscv

Last synced: 15 Oct 2024

https://github.com/ariya/hello-c90

Hello world in C90 (ANSI C) built for Intel/AMD, PowerPC, System z, ARM, MIPS, RISC-V

amd ansi-c arm c c90 clang continous-integration digital-mars gcc intel mips multi-platform powerpc ppc64 ppc64le risc-v riscv tcc visual-studio

Last synced: 09 Nov 2024

https://github.com/celebi-pkg/riscv-assembler

RISC-V Assembly code assembler package for Python.

assembler assembly instruction-set-architecture python risc-v riscv riscv-assembler

Last synced: 14 Oct 2024

https://github.com/michaeljclark/musl-riscv-toolchain

riscv-linux musl gcc toolchain bootstrap scripts

gcc musl musl-libc musl-riscv-toolchain risc-v riscv toolchain

Last synced: 05 Nov 2024

https://github.com/losfair/magicore

An out-of-order processor that supports multiple instruction sets.

cpu risc-v riscv

Last synced: 14 Oct 2024

https://github.com/rustsbi/rustsbi-hifive-unmatched

RustSBI support on SiFive FU740 board; FU740 is a five-core heterogeneous processor with four SiFive U74 cores, and one SiFive S7 core

risc-v riscv rust rustsbi sbi

Last synced: 11 Nov 2024

https://github.com/lupyuen/nuttx-tinyemu

Apache NuttX RTOS in the Web Browser: TinyEMU with VirtIO

nuttx riscv riscv64 tinyemu virtio wasm

Last synced: 14 Nov 2024

https://github.com/deadsy/rvdbg

RISC-V Debugger

debugger fe310 gd32v gd32vf103 gigadevice go golang jtag k210 kendryte risc-v riscv sifive

Last synced: 14 Nov 2024

https://github.com/lupyuen/bl602-rust-wrapper

Rust Wrapper for BL602 IoT SDK

bl602 bl604 macro riscv riscv32 rust

Last synced: 14 Nov 2024

https://github.com/lupyuen/lora-sx1262

LoRa Driver for Semtech SX1262 on Apache NuttX OS, Linux (PineDio USB Adapter) and BL602 IoT SDK (PineDio Stack BL604)

bl602 bl604 ch341 dkms linux lora pinebookpro pinedio riscv riscv32 spi

Last synced: 14 Nov 2024

https://github.com/leecannon/zriscv

RISC-V emulator in Zig

risc-v riscv zig ziglang

Last synced: 13 Nov 2024

https://github.com/0x5457/riscv-emulator

🖥️ a toy riscv emulator, written in Rust

emulator riscv rust

Last synced: 07 Nov 2024

https://github.com/eigenraven/rvasm

RISC-V Assembler

assembler extensible risc-v riscv rust

Last synced: 09 Nov 2024

https://github.com/lichtso/riscv-llvm-templates

Code templates to get started experimenting with the RISC-V LLVM toolchain

code-templates llvm risc-v riscv

Last synced: 07 Nov 2024

https://github.com/mikeroyal/assembly-guide

Assembly Guide

arm-assembly arm-assembly-language assembly assembly-language assembly-language-programming assembly-x86 assembly-x86-64 awesome awesome-list awesome-readme intel risc-v riscv x86 x86-64

Last synced: 03 Oct 2024

https://github.com/ccelio/riscv-hpmcounters

A simple utility for doing RISC-V HPM perf monitoring.

riscv

Last synced: 27 Oct 2024

https://github.com/mytechnotalent/hacking-risc-v

A FREE comprehensive step-by-step embedded RISC-V hacking tutorial covering RISC-V Embedded Software Development to Reverse Engineering.

arduino assembler assembly-language hack hacking platformio reverse-engineering risc-v riscv

Last synced: 10 Oct 2024

https://github.com/lupyuen/bl602-simulator

BL602 / BL604 Simulator in WebAssembly

bl602 embedded riscv rust webassembly

Last synced: 14 Nov 2024

https://github.com/socxin/risc-v

RISC-V Architecture

architecture qitas risc-v riscv

Last synced: 05 Nov 2024

https://github.com/new-tee-os/new-tee-os

A brand new OS that runs in various kinds of TEEs and supports Linux ABI

keystone-enclave riscv rust-os sgx-enclave

Last synced: 11 Nov 2024

https://github.com/mohanson/rv64

RISC-V RV64IMAFDC(RV64GC) Emulator

emulator golang riscv

Last synced: 07 Nov 2024

https://github.com/andelf/longan-nano-playground-rs

Longan Nano board(GD32VF103) examples, in Rust, under macOS. Bad Apple included.

longan-nano riscv rust-embedded

Last synced: 20 Oct 2024

https://github.com/lupyuen/pinecone-rust-mynewt

Mynewt + Rust for PineCone BL602 RISC-V Board

bl602 mynewt pinecone riscv rust

Last synced: 14 Nov 2024

https://github.com/platformio/platform-sifive

SiFive: development platform for PlatformIO

platformio platformio-platform risc-v riscv sifive

Last synced: 07 Oct 2024

https://github.com/leecannon/zig-sbi

Zig wrapper around the RISC-V SBI specification

opensbi osdev risc-v riscv riscv32 riscv64 sbi zig zig-package ziglang

Last synced: 17 Oct 2024

https://github.com/calint/tang-nano-9k--riscv--cache-psram

RISC-V implementation of rv32i for FPGA board Tang Nano 9K utilizing on-board burst PSRAM and flash

fpga riscv rv32i systemverilog tang-nano tang-nano-9k

Last synced: 11 Nov 2024

https://github.com/stupremee/spear

RISC-V emulator that is focused on correctness and tries to support as many features as possible.

emulator riscv riscv-emulator riscv-simulator rust

Last synced: 14 Oct 2024

https://github.com/michaeljclark/rv8-bench

rv8 benchmark suite

benchmarks musl-riscv-toolchain risc-v riscv riscv-qemu rv8 rv8-bench rv8-benchmarks

Last synced: 05 Nov 2024

https://github.com/rustsbi/sbi-spec

Definitions and constants in RISC-V Supervisor Binary Interface (RISC-V SBI)

riscv rust

Last synced: 11 Nov 2024

https://github.com/rustaceanskenya/driver-development-book

This is a book that explains driver development with Rust. It does so by procedurally creating a UART driver for a RISCV chip(an esp32c3)

driver-development embedded-rust esp32 esp32c3 riscv rust uart

Last synced: 10 Oct 2024

https://github.com/rnayabed/taurus

SDK for CDAC Vega Processors

cdac riscv riscv32 riscv64 sdk vega

Last synced: 12 Oct 2024

https://github.com/lsc-unicamp/processor-ci-controller

Controller module for RISC-V core CI/CD

fpga riscv verilog

Last synced: 13 Nov 2024

https://github.com/platformio/platform-riscv_gap

GreenWaves Technologies RISC-V GAP: development platform for PlatformIO

computer-vision deep-learning image-processing iot machine-learning neural-networks platformio platformio-platform pulp risc-v riscv

Last synced: 07 Oct 2024

https://github.com/kkinos/grvemu

RISC-V emulator for CLI written in Go.

cli emulator go riscv riscv-emulator

Last synced: 14 Nov 2024

https://github.com/martindisch/gd32vf103-demo

A small example for running Rust code on RISC-V

embedded embedded-rust gd32vf103 risc-v riscv

Last synced: 11 Oct 2024

https://github.com/platformio/platform-chipsalliance

CHIPS Alliance: development platform for PlatformIO

platformio platformio-platform risc-v riscv swerv

Last synced: 07 Oct 2024

https://github.com/howjmay/neon2rvv

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

aarch64 arm arm64 armv7 armv8 intrinsics neon riscv riscv64 rvv simd

Last synced: 15 Oct 2024

https://github.com/socxin/ch32v103

L2 R2：WCH RISC-V MCU(CH32V103)

mcu qitas risc-v risc-v3a riscv usb-host wch

Last synced: 05 Nov 2024

https://github.com/kassane/nuttx-dlang-app

D Apps for Apache NuttX RTOS and QEMU RISC-V

d dlang nuttx nuttx-apps qemu riscv

Last synced: 17 Oct 2024

https://github.com/deadsy/rvda

RISC-V Disassembler

disassembler go golang risc-v riscv

Last synced: 14 Nov 2024

https://github.com/jiegec/riscv-toolchain

Build bleeding edge riscv toolchain in Docker

riscv riscv-toolchain

Last synced: 09 Nov 2024

https://github.com/genodelabs/genode-riscv

RISC-V board support

cplusplus cpp genode microkernel osdev riscv

Last synced: 06 Nov 2024

https://github.com/playx18/asmkit

Assembler toolkit: encoding and decoding of various architectures

aarch64 assembler jit ppc64 riscv riscv64 x86

Last synced: 13 Nov 2024

https://github.com/five-embeddev/riscv-isa-data

Machine readable ISA data

risc-v riscv ruby yaml

Last synced: 07 Nov 2024

https://github.com/cbalint13/rvv-kernels

RISCV Vector Kernel C/LLVM-IR generator

int8 kernel llvm math riscv rvv tvm vector

Last synced: 14 Oct 2024

https://github.com/jesseopdenbrouw/thuas-riscv

The THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zba Zbs Sdext Sdtrig microcontroller

fpga hardware riscv riscv32 riscv32im rv32im soc

Last synced: 12 Nov 2024

https://github.com/lsc-unicamp/processor-ci-website

Processor CI project Website

mkdocs mkdocs-material riscv

Last synced: 14 Oct 2024

https://github.com/lupyuen/nuttx-riscv64

Apache NuttX RTOS on 64-bit RISC-V

nuttx riscv riscv64 rtos

Last synced: 14 Nov 2024

https://github.com/rnayabed/vegadude

Utility to program CDAC VEGA microprocessor powered boards

cdac cpp riscv vega

Last synced: 12 Oct 2024

https://github.com/riscj-blockits/riscj-computer-mod

computer-architecture computer-science cpu-emulator education fabric-mod fabricmc fabricmc-mod kit mima minecraft minecraft-mod processor-architecture processor-simulator risc-v riscv simulation

Last synced: 14 Oct 2024

https://github.com/lichtso/riscv

Risc-V: Dis/Assember and Emulator

c-plus-plus emulator riscv unmaintained

Last synced: 07 Nov 2024

https://github.com/rcore-os/riscv-sbi

Low level access to RISC-V Supervisor Binary Interface (SBI) implementations

riscv sbi

Last synced: 14 Nov 2024