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RISC-V
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
- GitHub: https://github.com/topics/riscv
- Wikipedia: https://en.wikipedia.org/wiki/riscv
- Aliases: risc-v, riscv-cpu, riscv-core,
- Last updated: 2024-12-18 00:26:47 UTC
- JSON Representation
https://github.com/hexdae/toolchains_riscv_gnu
RISC-V bazel toolchains for GCC compilation
bare-metal bazel gcc riscv toolchain
Last synced: 23 Nov 2024
https://github.com/michaeljclark/rv8-bench
rv8 benchmark suite
benchmarks musl-riscv-toolchain risc-v riscv riscv-qemu rv8 rv8-bench rv8-benchmarks
Last synced: 05 Nov 2024
https://github.com/platformio/platform-riscv_gap
GreenWaves Technologies RISC-V GAP: development platform for PlatformIO
computer-vision deep-learning image-processing iot machine-learning neural-networks platformio platformio-platform pulp risc-v riscv
Last synced: 07 Oct 2024
https://github.com/lsc-unicamp/processor-ci-controller
Controller module for RISC-V core CI/CD
Last synced: 13 Nov 2024
https://github.com/benmezger/strail
A kernel with support to the RISCV architecture
asm c kernel operating-system riscv unix
Last synced: 20 Nov 2024
https://github.com/kkinos/grvemu
RISC-V emulator for CLI written in Go.
cli emulator go riscv riscv-emulator
Last synced: 18 Dec 2024
https://github.com/martindisch/gd32vf103-demo
A small example for running Rust code on RISC-V
embedded embedded-rust gd32vf103 risc-v riscv
Last synced: 11 Oct 2024
https://github.com/platformio/platform-chipsalliance
CHIPS Alliance: development platform for PlatformIO
platformio platformio-platform risc-v riscv swerv
Last synced: 07 Oct 2024
https://github.com/wpmed92/riscyd2
A RISC-V based microcontroller
cpu hardware microcontroller python riscv verilog
Last synced: 09 Dec 2024
https://github.com/blessedrebus/riscv-rop-testbed
A testbed for RISCV vulnerable binaries that aims to produce meaningful fingerprints recognizable by a Control Flow integrity Machine Learning Algorithm.
buffer-overflow riscv rop security
Last synced: 01 Dec 2024
https://github.com/jiegec/riscv-toolchain
Build bleeding edge riscv toolchain in Docker
Last synced: 09 Nov 2024
https://github.com/lockblock-dev/vector
Risc-V ISA emulator
emulation emulator risc-v risc-v-emulator riscv rv32i
Last synced: 24 Nov 2024
https://github.com/deadsy/rvda
RISC-V Disassembler
disassembler go golang risc-v riscv
Last synced: 14 Nov 2024
https://github.com/kassane/nuttx-dlang-app
D Apps for Apache NuttX RTOS and QEMU RISC-V
d dlang nuttx nuttx-apps qemu riscv
Last synced: 17 Oct 2024
https://github.com/rnayabed/vegadude
Utility to program CDAC VEGA microprocessor powered boards
Last synced: 12 Oct 2024
https://github.com/lupyuen/nuttx-riscv64
Apache NuttX RTOS on 64-bit RISC-V
Last synced: 14 Nov 2024
https://github.com/genodelabs/genode-riscv
RISC-V board support
cplusplus cpp genode microkernel osdev riscv
Last synced: 06 Nov 2024
https://github.com/lsc-unicamp/processor-ci-website
Processor CI project Website
Last synced: 14 Oct 2024
https://github.com/lichtso/riscv
Risc-V: Dis/Assember and Emulator
c-plus-plus emulator riscv unmaintained
Last synced: 07 Nov 2024
https://github.com/ahmedheakl/asm2asm
From CISC to RISC: Language-Model Guided Assembly Transpilation
arm64 assembly assembly-benchmark evaluation llm riscv training transpilation
Last synced: 21 Dec 2024
https://github.com/coastalwhite/pulpino-top-level-cw305
The top-level Verilog files for the CW305 to run and communicate with the RISC-V PULPINO core
Last synced: 22 Nov 2024
https://github.com/rcore-os/riscv-sbi
Low level access to RISC-V Supervisor Binary Interface (SBI) implementations
Last synced: 14 Nov 2024
https://github.com/platformio/platform-openhw
OpenHW Group: development platform for PlatformIO
platformio platformio-platform risc-v riscv
Last synced: 07 Oct 2024
https://github.com/mariovilar/matematiques-enginyeria-informatica
Repositori dels meus apunts, exercicis i projectes en el doble grau de Matemàtiques i Enginyeria Informàtica (UB)
abstract-algebra class-notes computer-design computer-science data-structures-and-algorithms differential-calculus geometry integral-calculus linear-algebra mathematics number-theory numerical-methods object-oriented-programming riscv software-design topology
Last synced: 24 Nov 2024
https://github.com/nmeum/riscv-utils
Scheme utility procedures for the RISC-V instruction set architecture
Last synced: 06 Nov 2024
https://github.com/zyedidia/rvsym
A small RISC-V symbolic execution engine
riscv symbolic-execution symbolic-execution-engine
Last synced: 15 Nov 2024
https://github.com/smoothhacker/bn_riscv64
An architecture plugin for RISC-V 64I
binary-ninja binaryninja risc-v riscv
Last synced: 19 Nov 2024
https://github.com/jn513/grande-risco-5
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
arquitetura fpga risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/caseywebb/mayfly
Environmental monitoring for Aquaculture and Hydroponics
aquaculture aquaponics atlas-scientific circuitpython environmental-monitoring esp32 esp32-s2 hydroponics iot riscv ulp
Last synced: 11 Dec 2024
https://github.com/nuclei-software/nuclei-ai-library
Nuclei AI Library Optimized For RISC-V Vector
Last synced: 01 Dec 2024
https://github.com/jn513/pequeno-risco-5
Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.
arquitetura risc-v riscv riscv32 verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/yjl9903/minimoonbit-moca
Mini Moonbit implementation from 摩卡猫猫
compilers javascript minimoonbit moonbit programming-language riscv wasm
Last synced: 03 Dec 2024
https://github.com/jn513/risco-5s
RISC-V Simulator with RV32IM implementation, built during a few days off.
riscv riscv-assembly riscv-emulator riscv-simulator riscv32 riscv32i
Last synced: 15 Dec 2024
https://github.com/ydrmaster/aclint
Provide structs and methods to operate riscv aclint device.
Last synced: 20 Nov 2024
https://github.com/ydrmaster/plic
Provide structs and methods to operate riscv plic device.
Last synced: 20 Nov 2024
https://github.com/max22-/rv32
RISC-V (32-bit) emulator, in C89
c89 emulator risc-v risc-v-emulator riscv simulator
Last synced: 12 Oct 2024
https://github.com/m00nwtchr/oc2_hello_world
Open Computers II (RISC-V Musl Linux) Hello World Rust example, made very small
linux minecraft musl oc2 opencomputers risc-v riscv rust-lang rustlang
Last synced: 03 Dec 2024
https://github.com/riscv-mcu/n100_ses_project
SEGGER Embedded Studio Projects For Nuclei N100 Series
nuclei riscv segger-embedded-studio
Last synced: 09 Nov 2024
https://github.com/lebrancconvas/typescript-for-concept
Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).
computer-architecture cpu digital-circuit fpga fpga-programming low-byte-productions low-level memory playground-project risc-v riscv typescript virtual-machine vm
Last synced: 11 Nov 2024
https://github.com/supercip971/riscyinterpret
little RISCV interpreter
interpreter risc riscv riscv64
Last synced: 22 Dec 2024
https://github.com/255doesnotexist/boardtest
[WIP] A simple test framework for SBCs.
Last synced: 12 Nov 2024
https://github.com/raspiduino/arv32
A port of mini-rv32ima to Arduino UNO. Original code is from https://github.com/cnlohr/mini-rv32ima
arduino arduino-uno avr emulator linux riscv
Last synced: 08 Dec 2024
https://github.com/max1220/terrisc
A very WIP RISC-V emulator written in the terra language
emulator risc-v riscv riscv-emulator riscv64
Last synced: 07 Dec 2024
https://github.com/d901203/rv2llvm
Static Binary Translator RISC-V to LLVM IR
binary-translation elf go golang llvm llvm-ir risc-v riscv
Last synced: 14 Nov 2024
https://github.com/sekky61/riscv-sim
Web-based RISC-V superscalar simulator
Last synced: 08 Nov 2024
https://github.com/mc-cat-tty/riscv_experiments
Playing around with RISC-V assembly language.
assembly gcc-complier gcc-cross-compiler qemu qemu-riscv riscv riscv-emulator riscv64
Last synced: 15 Dec 2024
https://github.com/jasonbrave/microsoc
RISC-V SoC
microcontroller risc-v riscv soc system-on-chip systemverilog uart verilog
Last synced: 20 Dec 2024
https://github.com/ydrmaster/sifive-test-device
Provide definition of SiFive test device
Last synced: 20 Nov 2024
https://github.com/kodraus/hifive1-revb-template
A Cargo template for running Rust on RISC-V based HiFive1 boards
Last synced: 15 Nov 2024
https://github.com/stovent/dyriscvic
A RISC-V assembler, disassembler and interpreter (and maybe later JIT) written in Rust.
emulation interpreter risc-v riscv rust virtual-machine
Last synced: 24 Nov 2024
https://github.com/blessedrebus/riscv-attacks
Security analysis for the RISC-V ISA
bof cybersecurity embedded-systems risc-v riscv rop
Last synced: 01 Dec 2024
https://github.com/risceirb/risc-v-processor
Processor RISC-V and application
assembly assembly-risc assembly-risc-v branch-predictor enseirb enseirb-matmeca modelsim monocycle-processor pipeline pipeline-processor processor risc-v risc-v-architecture risc-v-architectures risc-v-assembly riscv ufsm
Last synced: 21 Nov 2024
https://github.com/xigh/rvdis-rs
RISCV RV32/64 very simple disassembler with ELF support
disassembler risc-v riscv rust
Last synced: 10 Nov 2024
https://github.com/jn513/baby-risco-5
Multi-cycle RISC-V processor with RV32E implementation
riscv riscv32 riscv32e verilog verilog-hdl
Last synced: 15 Dec 2024
https://github.com/m-tmatma/riscv-yocto
build environment for https://github.com/riscv/meta-riscv
Last synced: 07 Nov 2024
https://github.com/maxbubblegum47/tutorato_architettura
Materiale tutorato Architettura dei Calcolatori. Esercizi sul simulatore logisim e rars in assembly per RISCV
assembly logisim logisim-alu rars riscv riscv-assembly riscv32
Last synced: 29 Nov 2024
https://github.com/tmahlburg/mriscv
simple, modular rv32i implementation (WIP)
risc-v riscv riscv32 rv32i verilog verilog-hdl
Last synced: 16 Nov 2024
https://github.com/wpmed92/takerisc
A RISC-V RV32I Core written in TL-Verilog
hardware riscv riscv32 tl-verilog verilog
Last synced: 09 Dec 2024
https://github.com/mjaow/xv6-riscv-fall19
mit 6.828, an unix v6 like operating system
mit6828 operating-system riscv unix-v6 xv6
Last synced: 16 Dec 2024
https://github.com/justxuewei/project-rcore
Yet another rCore implementation by justxuewei
Last synced: 06 Dec 2024
https://github.com/rmacnak/riscv-tools
RISC-V assembler, disassembler and simulator suitable for a JIT.
Last synced: 17 Nov 2024
https://github.com/riscv-mcu/nuclei_vp
Nuclei Virtual Platform
qbox riscv systemc tlm2 virtual-platform
Last synced: 09 Nov 2024
https://github.com/nuclei-software/nuclei-tool-guide
Nuclei Tools(IDE/Toolchain/Qemu/OpenOCD/Xlmodel) Guide
documentation nuclei riscv tools
Last synced: 01 Dec 2024
https://github.com/cvut/comparch
Computer Architectures ČVUT Guidepost
computer-architecture education guidepos risc-v riscv
Last synced: 09 Nov 2024
https://github.com/64kramsystem/parsec-riscv-performance-testing
Program for setting up and running the PARSEC suite on an emulated RISC-V environment, used for my coauthored research paper.
bash emulation parsec-benchmark performance qemu riscv shell-script
Last synced: 18 Dec 2024
https://github.com/lupyuen/nuttx-purescript-parser
Parsing Apache NuttX RTOS Logs with PureScript
bl808 nuttx ox64 purescript riscv riscv64
Last synced: 14 Nov 2024
https://github.com/m3y54m/pcb-esp-c3-13-breakout-board
ESP-C3-13 Breakout Board
altium ble bluetooth breakout-board esp32 esp32-c3 pcb riscv wifi
Last synced: 20 Nov 2024
https://github.com/skpro-glitch/shorthand-risc
This is a simplified assembly language with a tabular structured instruction set. This is meant for easy learning and fast implementation of assembly languages in microprocessors and microcontrollers. - Soham Kapur, VIT Chennai
assembler assembly assembly-language assembly-language-programming compiler compiler-construction compiler-design compiler-optimization compiler-principles compilers risc risc-processor risc-v riscv shorthand shorthand-notation shorthand-syntax
Last synced: 21 Nov 2024
https://github.com/cosecseccot/riscv32i-assembler
A custom Assembler for RISCV32I ISA
assembler assembly assembly-language risc-v riscv riscv32
Last synced: 17 Nov 2024
https://github.com/shiritai/aias-lab6-spring-2024
Lab6 of AI computing Architecture and System (2024 spring) around riscv emulator and implementation of fibonacci, sudoku (2x2) and maxpool in RISC-V
assembly fibonacci maxpool2d riscv riscv-emulator sudoku
Last synced: 08 Nov 2024
